0a74246fb9
Because int and not InstSeqNum was used in a couple of places, you can overflow the int type and thus get wierd bugs when the sequence number is negative (or some wierd value)
340 lines
11 KiB
C++
340 lines
11 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include "config/the_isa.hh"
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#include "cpu/inorder/resources/fetch_seq_unit.hh"
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#include "cpu/inorder/resource_pool.hh"
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using namespace std;
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using namespace TheISA;
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using namespace ThePipeline;
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FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu,
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ThePipeline::Params *params)
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: Resource(res_name, res_id, res_width, res_latency, _cpu),
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instSize(sizeof(MachInst))
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{
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for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
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pcValid[tid] = false;
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pcBlockStage[tid] = 0;
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squashSeqNum[tid] = (InstSeqNum)-1;
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lastSquashCycle[tid] = 0;
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}
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}
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FetchSeqUnit::~FetchSeqUnit()
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{
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delete [] resourceEvent;
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}
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void
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FetchSeqUnit::init()
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{
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resourceEvent = new FetchSeqEvent[width];
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for (int i = 0; i < width; i++) {
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reqs[i] = new ResourceRequest(this);
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}
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initSlots();
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}
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void
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FetchSeqUnit::execute(int slot_num)
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{
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ResourceRequest* fs_req = reqs[slot_num];
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DynInstPtr inst = fs_req->inst;
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ThreadID tid = inst->readTid();
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int stage_num = fs_req->getStageNum();
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InstSeqNum seq_num = inst->seqNum;
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid,
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pc[tid]);
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switch (fs_req->cmd)
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{
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case AssignNextPC:
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{
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if (pcValid[tid]) {
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inst->pcState(pc[tid]);
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inst->setMemAddr(pc[tid].instAddr());
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// Advance to next PC (typically PC + 4)
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pc[tid].advance();
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inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to "
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"PC %s\n", tid, inst->seqNum, inst->pcState());
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fs_req->done();
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} else {
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DPRINTF(InOrderStall, "STALL: [tid:%i]: NPC not valid\n", tid);
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fs_req->done(false);
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}
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}
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break;
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case UpdateTargetPC:
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{
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if (inst->isControl()) {
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// If it's a return, then we must wait for resolved address.
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if (inst->isReturn() && !inst->predTaken()) {
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cpu->pipelineStage[stage_num]->
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toPrevStages->stageBlock[stage_num][tid] = true;
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pcValid[tid] = false;
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pcBlockStage[tid] = stage_num;
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} else if (inst->isCondDelaySlot() && !inst->predTaken()) {
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// Not-Taken AND Conditional Control
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DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%s] "
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"Predicted Not-Taken Cond. Delay inst. Skipping "
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"delay slot and Updating PC to %s\n",
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tid, inst->seqNum, inst->pcState(),
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inst->readPredTarg());
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DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
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"start from stage %i, after [sn:%i].\n", tid,
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stage_num, seq_num);
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inst->bdelaySeqNum = seq_num;
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inst->squashingStage = stage_num;
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squashAfterInst(inst, stage_num, tid);
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} else if (!inst->isCondDelaySlot() && !inst->predTaken()) {
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// Not-Taken Control
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DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted "
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"Not-Taken Control "
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"inst. updating PC to %s\n", tid, inst->seqNum,
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inst->readPredTarg());
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#if ISA_HAS_DELAY_SLOT
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pc[tid] = inst->pcState();
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advancePC(pc[tid], inst->staticInst);
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#endif
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} else if (inst->predTaken()) {
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// Taken Control
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#if ISA_HAS_DELAY_SLOT
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pc[tid] = inst->readPredTarg();
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DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay"
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" slot target to PC %s\n", tid, inst->seqNum,
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inst->readPredTarg());
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inst->bdelaySeqNum = seq_num + 1;
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#else
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inst->bdelaySeqNum = seq_num;
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#endif
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inst->squashingStage = stage_num;
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DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
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"start from stage %i, after [sn:%i].\n",
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tid, stage_num, inst->bdelaySeqNum);
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// Do Squashing
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squashAfterInst(inst, stage_num, tid);
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}
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} else {
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DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Ignoring branch "
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"target update since then is not a control "
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"instruction.\n", tid, inst->seqNum);
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}
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fs_req->done();
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}
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break;
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default:
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fatal("Unrecognized command to %s", resName);
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}
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}
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inline void
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FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid)
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{
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// Squash In Pipeline Stage
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cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
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// Squash inside current resource, so if there needs to be fetching on
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// same cycle the fetch information will be correct.
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// Schedule Squash Through-out Resource Pool
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cpu->resPool->scheduleEvent(
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(InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
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}
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void
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FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
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InstSeqNum squash_seq_num, ThreadID tid)
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{
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i."
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"\n", tid, squash_stage);
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InstSeqNum done_seq_num = inst->bdelaySeqNum;
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// Handles the case where we are squashing because of something that is
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// not a branch...like a memory stall
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TheISA::PCState newPC;
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if (inst->isControl()) {
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newPC = inst->readPredTarg();
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} else {
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TheISA::PCState thisPC = inst->pcState();
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assert(inst->staticInst);
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advancePC(thisPC, inst->staticInst);
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newPC = thisPC;
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}
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if (squashSeqNum[tid] <= done_seq_num &&
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lastSquashCycle[tid] == curTick()) {
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, "
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"since there is an outstanding squash that is older.\n",
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tid, squash_stage);
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} else {
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squashSeqNum[tid] = done_seq_num;
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lastSquashCycle[tid] = curTick();
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// If The very next instruction number is the done seq. num,
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// then we haven't seen the delay slot yet ... if it isn't
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// the last done_seq_num then this is the delay slot inst.
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if (cpu->nextInstSeqNum(tid) != done_seq_num &&
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!inst->procDelaySlotOnMispred) {
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// Reset PC
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pc[tid] = newPC;
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#if ISA_HAS_DELAY_SLOT
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TheISA::advancePC(pc[tid], inst->staticInst);
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#endif
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %s.\n",
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tid, newPC);
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} else {
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assert(ISA_HAS_DELAY_SLOT);
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pc[tid] = (inst->procDelaySlotOnMispred) ?
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inst->branchTarget() : newPC;
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// Reset PC to Delay Slot Instruction
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if (inst->procDelaySlotOnMispred) {
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// Reset PC
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pc[tid] = newPC;
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}
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}
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// Unblock Any Stages Waiting for this information to be updated ...
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if (!pcValid[tid]) {
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cpu->pipelineStage[pcBlockStage[tid]]->
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toPrevStages->stageUnblock[pcBlockStage[tid]][tid] = true;
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}
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pcValid[tid] = true;
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}
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Resource::squash(inst, squash_stage, squash_seq_num, tid);
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}
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FetchSeqUnit::FetchSeqEvent::FetchSeqEvent()
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: ResourceEvent()
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{ }
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void
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FetchSeqUnit::FetchSeqEvent::process()
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{
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FetchSeqUnit* fs_res = dynamic_cast<FetchSeqUnit*>(resource);
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assert(fs_res);
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for (int i = 0; i < MaxThreads; i++) {
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fs_res->pc[i] = fs_res->cpu->pcState(i);
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC: %s.\n",
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fs_res->pc[i]);
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fs_res->pcValid[i] = true;
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}
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}
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void
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FetchSeqUnit::activateThread(ThreadID tid)
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{
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pcValid[tid] = true;
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pc[tid] = cpu->pcState(tid);
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cpu->fetchPriorityList.push_back(tid);
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Reading PC: %s.\n",
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tid, pc[tid]);
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}
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void
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FetchSeqUnit::deactivateThread(ThreadID tid)
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{
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pcValid[tid] = false;
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pcBlockStage[tid] = 0;
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squashSeqNum[tid] = (InstSeqNum)-1;
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lastSquashCycle[tid] = 0;
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list<ThreadID>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
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cpu->fetchPriorityList.end(),
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tid);
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if (thread_it != cpu->fetchPriorityList.end())
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cpu->fetchPriorityList.erase(thread_it);
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}
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void
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FetchSeqUnit::suspendThread(ThreadID tid)
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{
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deactivateThread(tid);
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}
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void
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FetchSeqUnit::updateAfterContextSwitch(DynInstPtr inst, ThreadID tid)
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{
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pcValid[tid] = true;
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if (cpu->thread[tid]->lastGradIsBranch) {
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/** This function assumes that the instruction causing the context
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* switch was right after the branch. Thus, if it's not, then
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* we are updating incorrectly here
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*/
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assert(cpu->nextInstAddr(tid) == inst->instAddr());
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pc[tid] = cpu->thread[tid]->lastBranchPC;
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} else {
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pc[tid] = inst->pcState();
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}
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assert(inst->staticInst);
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advancePC(pc[tid], inst->staticInst);
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating PCs due to Context Switch."
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"Assigning PC: %s.\n", tid, pc[tid]);
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}
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