203efba46a
Add support for the Ruby stride prefetcher to MESI_Three_Level. Change-Id: Id68935e2a7d3ccd0e22a59f43a15f167410632a2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27715 Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
96 lines
4.2 KiB
Plaintext
96 lines
4.2 KiB
Plaintext
/*
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* Copyright (c) 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2013 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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// Various class of messages that can be exchanged between the L0 and the L1
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// controllers.
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enumeration(CoherenceClass, desc="...") {
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GETX, desc="Get eXclusive";
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UPGRADE, desc="UPGRADE to exclusive";
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GETS, desc="Get Shared";
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GET_INSTR, desc="Get Instruction";
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INV_OWN, desc="Invalidate (own)";
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INV_ELSE, desc="Invalidate (else)";
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PUTX, desc="Replacement message";
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WB_ACK, desc="Writeback ack";
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// Request types for sending data and acks from L0 to L1 cache
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// when an invalidation message is received.
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INV_DATA;
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INV_ACK;
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DATA, desc="Data block for L1 cache in S state";
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DATA_EXCLUSIVE, desc="Data block for L1 cache in M/E state";
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ACK, desc="Generic invalidate ack";
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// This is a special case in which the L1 cache lost permissions to the
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// shared block before it got the data. So the L0 cache can use the data
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// but not store it.
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STALE_DATA;
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}
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// Class for messages sent between the L0 and the L1 controllers.
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structure(CoherenceMsg, desc="...", interface="Message") {
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Addr addr, desc="Physical address of the cache block";
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CoherenceClass Class, desc="Type of message (GetS, GetX, PutX, etc)";
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RubyAccessMode AccessMode, desc="user/supervisor access type";
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MachineID Sender, desc="What component sent this message";
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MachineID Dest, desc="What machine receives this message";
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MessageSizeType MessageSize, desc="size category of the message";
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DataBlock DataBlk, desc="Data for the cache line (if PUTX)";
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bool Dirty, default="false", desc="Dirty bit";
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PrefetchBit Prefetch, desc="Is this a prefetch request";
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bool functionalRead(Packet *pkt) {
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// Only PUTX messages contains the data block
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if (Class == CoherenceClass:PUTX) {
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return testAndRead(addr, DataBlk, pkt);
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}
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return false;
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}
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bool functionalWrite(Packet *pkt) {
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// No check on message type required since the protocol should
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// read data from those messages that contain the block
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return testAndWrite(addr, DataBlk, pkt);
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}
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}
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