Steve Reinhardt 0a02e3a764 Merge vm1.(none):/home/stever/bk/newmem-head ...

into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : a8efe71a50b9ae480c5ad0aabd7aa9ba22bc2968

2007-05-20 23:05:02 -07:00

..

arch

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

base

total should be the sum of the vector result of an operation,

2007-05-11 11:47:18 -07:00

cpu

Add new EventWrapper constructor that takes a Tick value

2007-05-20 21:43:01 -07:00

dev

Add new EventWrapper constructor that takes a Tick value

2007-05-20 21:43:01 -07:00

doxygen

Fix up doxygen.

2006-08-14 19:25:07 -04:00

kern

change the way dprintf works so the cache accesses required to fulfill the dprintf aren't show in between the Cycle: name:

2007-05-01 18:14:16 -04:00

mem

Merge vm1.(none):/home/stever/bk/newmem-head

2007-05-20 23:05:02 -07:00

python

PhysicalMemory has vector of uniform ports instead of one special one.

2007-05-19 00:24:34 -04:00

sim

Add new EventWrapper constructor that takes a Tick value

2007-05-20 21:43:01 -07:00

unittest

Quick program to time how long ccprintf takes to write

2007-02-07 22:02:09 -08:00

Doxyfile

Fix up doxygen.

2006-08-14 19:25:07 -04:00

SConscript

Completely re-work how the scons framework incorporates swig

2007-04-12 21:20:04 -07:00