08913caec2
This header is no longer used. Remove the places where it's included, and stop generating it. Also eliminate the now empty SPARC and Power versions of the header. Change-Id: I6ee66d39bc0218d1d9b9b7db3b350134ef03251d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39337 Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
97 lines
3.5 KiB
C++
97 lines
3.5 KiB
C++
/*
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* Copyright (c) 2011, 2016 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "kern/linux/events.hh"
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#include <sstream>
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#include "base/output.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "kern/linux/helpers.hh"
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#include "kern/system_events.hh"
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#include "sim/core.hh"
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#include "sim/system.hh"
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namespace Linux
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{
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void
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DmesgDump::process(ThreadContext *tc)
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{
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inform("Dumping kernel dmesg buffer to %s...\n", fname);
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OutputStream *os = simout.create(fname);
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dumpDmesg(tc, *os->stream());
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simout.close(os);
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warn(descr());
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}
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void
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KernelPanic::process(ThreadContext *tc)
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{
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inform("Dumping kernel dmesg buffer to %s...\n", fname);
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OutputStream *os = simout.create(fname);
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dumpDmesg(tc, *os->stream());
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simout.close(os);
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panic(descr());
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}
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void
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onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t time)
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{
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// convert parameter to ns
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if (div)
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time /= div;
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time *= mul;
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// Currently, only ARM full-system simulation uses UDelayEvents to skip
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// __delay and __loop_delay functions. One form involves setting quiesce
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// time to 0 with the assumption that quiesce will not happen. To avoid
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// the quiesce handling in this case, only execute the quiesce if time > 0.
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if (time > 0)
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tc->quiesceTick(curTick() + SimClock::Int::ns * time);
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}
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} // namespace linux
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