Jordi Vaquero 0860a91b11 arch-arm: FCVTZS instruction returns sign extension ...

This patch fix Fcvtzs instruction adding sign extension instead of
zero extension

Change-Id: I28cdca432fa6baa8a524de4c431f492f23f0e9a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28229
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-05-04 21:12:25 +00:00

..

arch

arch-arm: FCVTZS instruction returns sign extension

2020-05-04 21:12:25 +00:00

base

base, python, sim: Add support for resoving a stat using its name

2020-04-29 21:02:32 +00:00

cpu

cpu: Don't assert on branch target addresses

2020-05-01 04:45:31 +00:00

dev

dev-hsa: Add HSA device and HSA packet processor

2020-04-30 15:54:38 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

misc: Delete authors lists from documentation related files.

2020-02-17 21:50:09 +00:00

gpu-compute

base,arch-hsail: Fix GPU build

2020-04-03 21:51:57 +00:00

kern

base,arch,sim,cpu: Move object file loader components into a namespace.

2020-04-22 06:08:54 +00:00

learning_gem5

mem-ruby: Replace SLICC queueMemory calls with enqueue

2020-04-08 23:40:57 +00:00

mem

mem-cache: Fixes to PIF prefetcher

2020-05-04 10:29:03 +00:00

proto

misc: Use the protobuf version to choose between ByteSize(Long).

2020-04-29 21:46:11 +00:00

python

python: Fix compareVersions for python 3.

2020-04-30 22:16:51 +00:00

sim

sim: Inheritance fixes in varargs

2020-04-30 09:14:42 +00:00

systemc

misc: Replace __metaclass__ with six.add_metaclass

2020-03-10 09:35:56 +00:00

unittest

base,arch,sim,cpu: Move object file loader components into a namespace.

2020-04-22 06:08:54 +00:00

Doxyfile

misc: Updated Doxygen to state version as v19.0.0.0

2020-02-16 02:50:20 +00:00

SConscript

scons: Build the marshal binary in a bare minimum environment

2020-05-01 23:23:52 +00:00