Derek Christ
803f9f5aa7
Add DRAMSys as a new AbstractMemorySystem to the gem5 stdlib.
Also, provide convenient subclasses with predefined DRAMSys
configurations.
Add two new stdlib examples:
- dramsys-traffic.py: Demonstrates the usage of DRAMSys
using the stdlib TrafficGenerators
- arm-hello-dramsys.py: A variant of the arm-hello.py
script that uses DRAMSys as it's memory.
These DRAMSys memory components are only compiled into the standard
library if DRAMSys is not compiled into gem5.
Change-Id: I9db87c41fbd9c28bc44e9d6bde13fc225dc16be9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62914
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
91 lines
3.2 KiB
C++
91 lines
3.2 KiB
C++
/*
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* Copyright (c) 2022 Fraunhofer IESE
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_DRAMSYS_WRAPPER_HH__
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#define __MEM_DRAMSYS_WRAPPER_HH__
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#include <iostream>
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#include <memory>
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#include "DRAMSysConfiguration.h"
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#include "mem/abstract_mem.hh"
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#include "params/DRAMSys.hh"
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#include "sim/core.hh"
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#include "simulation/DRAMSysRecordable.h"
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#include "systemc/core/kernel.hh"
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#include "systemc/ext/core/sc_module_name.hh"
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#include "systemc/ext/systemc"
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#include "systemc/ext/tlm"
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#include "systemc/ext/tlm_utils/simple_target_socket.h"
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#include "systemc/tlm_port_wrapper.hh"
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namespace gem5
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{
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namespace memory
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{
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class DRAMSysWrapper : public sc_core::sc_module
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{
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friend class DRAMSys;
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public:
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SC_HAS_PROCESS(DRAMSysWrapper);
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DRAMSysWrapper(sc_core::sc_module_name name,
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DRAMSysConfiguration::Configuration const &config,
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bool recordable,
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AddrRange range);
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private:
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static std::shared_ptr<::DRAMSys>
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instantiateDRAMSys(bool recordable,
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DRAMSysConfiguration::Configuration const &config);
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tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
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tlm::tlm_phase &phase,
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sc_core::sc_time &fwDelay);
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tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload,
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tlm::tlm_phase &phase,
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sc_core::sc_time &bwDelay);
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unsigned int transport_dbg(tlm::tlm_generic_payload &trans);
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tlm_utils::simple_initiator_socket<DRAMSysWrapper> iSocket;
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tlm_utils::simple_target_socket<DRAMSysWrapper> tSocket;
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std::shared_ptr<::DRAMSys> dramsys;
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AddrRange range;
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};
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} // namespace memory
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} // namespace gem5
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#endif // __MEM_DRAMSYS_WRAPPER_HH__
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