6bbb28a5b3
Change-Id: Id3628d34adccf8cc1044195b7209f3b01f061c93 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25454 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
99 lines
4.0 KiB
Python
99 lines
4.0 KiB
Python
# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import m5
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from m5.objects import *
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import argparse
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parser = argparse.ArgumentParser(description='Simple memory tester')
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parser.add_argument('--bandwidth', default=None)
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parser.add_argument('--latency', default=None)
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parser.add_argument('--latency_var', default=None)
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args = parser.parse_args()
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# even if this is only a traffic generator, call it cpu to make sure
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# the scripts are happy
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try:
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cpu = TrafficGen(
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config_file=os.path.join(os.path.dirname(os.path.abspath(__file__)),
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"tgen-simple-mem.cfg"))
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except NameError:
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m5.fatal("protobuf required for simple memory test")
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class MyMem(SimpleMemory):
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if args.bandwidth:
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bandwidth = args.bandwidth
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if args.latency:
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latency = args.latency
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if args.latency_var:
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latency_var = args.latency_var
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# system simulated
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system = System(cpu = cpu, physmem = MyMem(),
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membus = IOXBar(width = 16),
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clk_domain = SrcClockDomain(clock = '1GHz',
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voltage_domain =
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VoltageDomain()))
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# add a communication monitor, and also trace all the packets and
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# calculate and verify stack distance
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system.monitor = CommMonitor()
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system.monitor.trace = MemTraceProbe(trace_file = "monitor.ptrc.gz")
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system.monitor.stackdist = StackDistProbe(verify = True)
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# connect the traffic generator to the bus via a communication monitor
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system.cpu.port = system.monitor.slave
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system.monitor.master = system.membus.slave
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# connect the system port even if it is not used in this example
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system.system_port = system.membus.slave
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# connect memory to the membus
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system.physmem.port = system.membus.master
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# -----------------------
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# run simulation
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# -----------------------
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root = Root(full_system = False, system = system)
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root.system.mem_mode = 'timing'
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m5.instantiate()
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exit_event = m5.simulate(100000000000)
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if exit_event.getCause() != "simulate() limit reached":
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exit(1)
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