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06bb6a473157a204bb7e77ea28e618aa08d2d811
gem5/src/sim
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Steve Reinhardt 06bb6a4731 syscall emulation: fix fast build issue 
Surprisingly gcc will complain about unused variables even
inside an 'if (false)' block.

I thought I had tested this previously, but apparently not.
2014-07-19 02:06:22 -07:00
..
probe
scons: Fixes uninitialized warnings issued by clang
2014-03-07 15:56:23 -05:00
arguments.cc
GetArgument: Rework getArgument so that X86_FS compiles again.
2010-10-15 23:57:06 -07:00
arguments.hh
arch: Resurrect the NOISA build target and rename it NULL
2013-09-04 13:22:57 -04:00
async.cc
base: Fix race in PollQueue and remove SIGALRM workaround
2013-11-29 14:36:10 +01:00
async.hh
base: Fix race in PollQueue and remove SIGALRM workaround
2013-11-29 14:36:10 +01:00
BaseTLB.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
byteswap.hh
gcc: Clean-up of non-C++0x compliant code, first steps
2012-03-19 06:36:09 -04:00
clock_domain.cc
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
clock_domain.hh
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
ClockDomain.py
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
clocked_object.hh
sim: More rigorous clocking comments
2014-06-09 22:01:16 -05:00
ClockedObject.py
sim: Add the notion of clock domains to all ClockedObjects
2013-06-27 05:49:49 -04:00
core.cc
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
core.hh
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
debug.cc
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
debug.hh
sim: Clarify the difference between tracing and debugging
2013-11-01 11:56:13 -04:00
drain.cc
sim: Move the draining interface into a separate base class
2012-11-02 11:32:01 -05:00
drain.hh
scons: Add warning for missing declarations
2013-02-19 05:56:07 -05:00
dvfs_handler.cc
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
dvfs_handler.hh
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
DVFSHandler.py
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
eventq_impl.hh
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
eventq.cc
sim: Add the ability to lock and migrate between event queues
2014-04-03 11:22:49 +02:00
eventq.hh
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
fault_fwd.hh
copyright: clean up copyright blocks
2011-06-02 14:36:35 -07:00
faults.cc
SE/FS: Get rid of FULL_SYSTEM in sim.
2011-11-02 02:11:14 -07:00
faults.hh
SE/FS: Get rid of includes of config/full_system.hh.
2011-11-18 02:20:22 -08:00
full_system.hh
clang: Fix recently introduced clang compilation errors
2012-03-19 06:35:04 -04:00
global_event.cc
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
global_event.hh
sim: Add the ability to lock and migrate between event queues
2014-04-03 11:22:49 +02:00
init.cc
sim: Use correct unit for abort message
2014-04-23 05:18:27 -04:00
init.hh
scons: Add warning for missing declarations
2013-02-19 05:56:07 -05:00
insttracer.hh
cpu: Allow setWhen on trace objects
2014-05-09 18:58:47 -04:00
InstTracer.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
main.cc
libm5: Create a libm5 static library for embedding m5.
2008-08-03 18:19:54 -07:00
microcode_rom.hh
CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
2008-10-12 15:59:21 -07:00
process_impl.hh
MEM: Make port proxies use references rather than pointers
2012-02-24 11:45:30 -05:00
process.cc
arm: Add support for ARMv8 (AArch64 & AArch32)
2014-01-24 15:29:34 -06:00
process.hh
process: add progName() virtual function
2012-08-06 16:55:34 -07:00
Process.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
pseudo_inst.cc
sim: added option to serialize SimLoopExitEvent
2013-10-31 13:41:13 -05:00
pseudo_inst.hh
sim: Add a helper function to execute pseudo instructions
2013-04-22 13:20:32 -04:00
root.cc
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
root.hh
sim: Provide a framework for detecting out of data checkpoints and migrating them.
2012-06-05 01:23:10 -04:00
Root.py
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
SConscript
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
serialize.cc
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
serialize.hh
util: Add DVFS perfLevel to checkpoint upgrade script
2014-07-01 11:58:22 -04:00
sim_events.cc
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
sim_events.hh
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
sim_exit.hh
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
sim_object.cc
base: add support for probe points and common probes
2014-01-24 15:29:30 -06:00
sim_object.hh
base: add support for probe points and common probes
2014-01-24 15:29:30 -06:00
simulate.cc
sim: Add the ability to lock and migrate between event queues
2014-04-03 11:22:49 +02:00
simulate.hh
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
stat_control.cc
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
stat_control.hh
scons: Add warning for missing declarations
2013-02-19 05:56:07 -05:00
stats.hh
stats: make simTicks and simFreq accessible from stats.hh
2010-04-18 13:23:25 -07:00
syscall_emul.cc
syscall emulation: fix fast build issue
2014-07-19 02:06:22 -07:00
syscall_emul.hh
sim, arm: implement more of the at variety syscalls
2014-04-17 16:55:05 -05:00
syscallreturn.hh
syscall emulation: clean up & comment SyscallReturn
2014-05-12 14:23:31 -07:00
system.cc
sim: remove unused MemoryModeStrings array
2014-07-18 22:05:51 -07:00
system.hh
sim: remove unused MemoryModeStrings array
2014-07-18 22:05:51 -07:00
System.py
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
tlb.cc
arch: Create a method to finalize physical addresses
2013-06-03 13:55:41 +02:00
tlb.hh
arch, arm: Preserve TLB bootUncacheability when switching CPUs
2014-05-09 18:58:47 -04:00
voltage_domain.cc
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
voltage_domain.hh
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
VoltageDomain.py
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
vptr.hh
MEM: Make port proxies use references rather than pointers
2012-02-24 11:45:30 -05:00