Andreas Hansson 0622f30961 mem: Add predecessor to SenderState base class ...

This patch adds a predecessor field to the SenderState base class to
make the process of linking them up more uniform, and enable a
traversal of the stack without knowing the specific type of the
subclasses.

There are a number of simplifications done as part of changing the
SenderState, particularly in the RubyTest.

2013-02-19 05:56:05 -05:00

..

alpha

x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch

2013-01-22 00:10:10 -06:00

arm

loader: add a flattened device tree blob (dtb) object

2013-02-15 18:48:59 -05:00

generic

arch: Fix broken M5VarArgsFault initialization

2013-01-07 13:05:38 -05:00

mips

x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch

2013-01-22 00:10:10 -06:00

noisa

cpu: add separate stats for insts/ops both globally and per cpu model

2012-02-12 16:07:39 -06:00

power

x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch

2013-01-22 00:10:10 -06:00

sparc

x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch

2013-01-22 00:10:10 -06:00

x86

mem: Add predecessor to SenderState base class

2013-02-19 05:56:05 -05:00

isa_parser.py

O3: Clean up the O3 structures and try to pack them a bit better.

2012-06-05 01:23:09 -04:00

micro_asm_test.py

Add a second section to make sure the ROM is extended properly.

2007-05-31 22:21:21 +00:00

micro_asm.py

scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access

2009-09-22 15:24:16 -07:00

SConscript

CPU: Merge the predecoder and decoder.

2012-05-26 13:44:46 -07:00