gem5/src/dev/x86/intdev.hh

/*
 * Copyright (c) 2012 ARM Limited
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2008 The Regents of The University of Michigan
 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
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 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
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 */

#ifndef __DEV_X86_INTDEV_HH__
#define __DEV_X86_INTDEV_HH__

#include <cassert>
#include <functional>
#include <string>

#include "base/cast.hh"
#include "mem/tport.hh"
#include "sim/sim_object.hh"

namespace X86ISA
{

template <class Device>
class IntSlavePort : public SimpleTimingPort
{
    Device * device;

  public:
    IntSlavePort(const std::string& _name, SimObject* _parent,
                 Device* dev) :
        SimpleTimingPort(_name, _parent), device(dev)
    {
    }

    AddrRangeList
    getAddrRanges() const
    {
        return device->getIntAddrRange();
    }

    Tick
    recvAtomic(PacketPtr pkt)
    {
        panic_if(pkt->cmd != MemCmd::WriteReq,
                "%s received unexpected command %s from %s.\n",
                name(), pkt->cmd.toString(), getPeer());
        pkt->headerDelay = pkt->payloadDelay = 0;
        return device->recvMessage(pkt);
    }
};

template<class T>
PacketPtr
buildIntPacket(Addr addr, T payload)
{
    RequestPtr req = std::make_shared<Request>(
        addr, sizeof(T), Request::UNCACHEABLE, Request::intMasterId);
    PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
    pkt->allocate();
    pkt->setRaw<T>(payload);
    return pkt;
}

template <class Device>
class IntMasterPort : public QueuedMasterPort
{
  private:
    ReqPacketQueue reqQueue;
    SnoopRespPacketQueue snoopRespQueue;

    Device* device;
    Tick latency;

    typedef std::function<void(PacketPtr)> OnCompletionFunc;
    struct OnCompletion : public Packet::SenderState
    {
        OnCompletionFunc func;
        OnCompletion(OnCompletionFunc _func) : func(_func) {}
    };
    // If nothing extra needs to happen, just clean up the packet.
    static void defaultOnCompletion(PacketPtr pkt) { delete pkt; }

  public:
    IntMasterPort(const std::string& _name, SimObject* _parent,
                  Device* dev, Tick _latency) :
        QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue),
        reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),
        device(dev), latency(_latency)
    {
    }

    bool
    recvTimingResp(PacketPtr pkt) override
    {
        assert(pkt->isResponse());
        auto *oc = safe_cast<OnCompletion *>(pkt->popSenderState());
        oc->func(pkt);
        delete oc;
        return true;
    }

    void
    sendMessage(PacketPtr pkt, bool timing,
            OnCompletionFunc func=defaultOnCompletion)
    {
        if (timing) {
            pkt->pushSenderState(new OnCompletion(func));
            schedTimingReq(pkt, curTick() + latency);
            // The target handles cleaning up the packet in timing mode.
        } else {
            // ignore the latency involved in the atomic transaction
            sendAtomic(pkt);
            func(pkt);
        }
    }
};

} // namespace X86ISA

#endif //__DEV_X86_INTDEV_HH__