Xuan Hu 74fcc4d6b7 arch-riscv: refactor bitfields of insts ...

+ move bitfields of ExtMachInst defined in bitfields.hh
  to types.hh

Change-Id: Ic25e2fd1a887f87231268a4449d8755593919a0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68417
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Roger Chang <rogerycchang@google.com>

2023-04-26 00:41:06 +00:00

..

arm

util: Teach the m5 utility's scons how to run unit tests.

2020-12-04 01:39:34 +00:00

arm64

util: Rename the aarch64 m5 util version to arm64.

2020-12-04 11:13:50 +00:00

riscv

arch-riscv: refactor bitfields of insts

2023-04-26 00:41:06 +00:00

sparc

util: Teach the m5 utility's scons how to run unit tests.

2020-12-04 01:39:34 +00:00

thumb

util: Teach the m5 utility's scons how to run unit tests.

2020-12-04 01:39:34 +00:00

x86

util: Teach the m5 utility's scons how to run unit tests.

2020-12-04 01:39:34 +00:00