a00f6d67d4
This is an initial step towards making TLBI shareable issue memory operations (generating DVM messages) JIRA: https://gem5.atlassian.net/browse/GEM5-1097 Change-Id: I90d4ec6f57f98860d082b393080290cd245af64f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56595 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
1054 lines
34 KiB
C++
1054 lines
34 KiB
C++
/*
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* Copyright (c) 2010, 2012-2021 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ARM_ISA_HH__
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#define __ARCH_ARM_ISA_HH__
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#include "arch/arm/isa_device.hh"
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#include "arch/arm/mmu.hh"
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#include "arch/arm/pcstate.hh"
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#include "arch/arm/regs/int.hh"
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#include "arch/arm/regs/misc.hh"
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#include "arch/arm/self_debug.hh"
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#include "arch/arm/system.hh"
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#include "arch/arm/types.hh"
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#include "arch/arm/utility.hh"
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#include "arch/generic/isa.hh"
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#include "debug/Checkpoint.hh"
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#include "enums/DecoderFlavor.hh"
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#include "sim/sim_object.hh"
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namespace gem5
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{
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struct ArmISAParams;
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struct DummyArmISADeviceParams;
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class Checkpoint;
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class EventManager;
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namespace ArmISA
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{
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class ISA : public BaseISA
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{
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protected:
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// Parent system
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ArmSystem *system;
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// Micro Architecture
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const enums::DecoderFlavor _decoderFlavor;
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/** Dummy device for to handle non-existing ISA devices */
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DummyISADevice dummyDevice;
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// PMU belonging to this ISA
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BaseISADevice *pmu;
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// Generic timer interface belonging to this ISA
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std::unique_ptr<BaseISADevice> timer;
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// GICv3 CPU interface belonging to this ISA
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std::unique_ptr<BaseISADevice> gicv3CpuInterface;
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// Cached copies of system-level properties
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bool highestELIs64;
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bool haveLargeAsid64;
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uint8_t physAddrRange;
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/** SVE vector length in quadwords */
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unsigned sveVL;
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/** This could be either a FS or a SE release */
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const ArmRelease *release;
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/**
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* If true, accesses to IMPLEMENTATION DEFINED registers are treated
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* as NOP hence not causing UNDEFINED INSTRUCTION.
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*/
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bool impdefAsNop;
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bool afterStartup;
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SelfDebug * selfDebug;
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/** MiscReg metadata **/
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struct MiscRegLUTEntry
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{
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uint32_t lower; // Lower half mapped to this register
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uint32_t upper; // Upper half mapped to this register
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uint64_t _reset; // value taken on reset (i.e. initialization)
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uint64_t _res0; // reserved
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uint64_t _res1; // reserved
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uint64_t _raz; // read as zero (fixed at 0)
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uint64_t _rao; // read as one (fixed at 1)
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public:
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MiscRegLUTEntry() :
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lower(0), upper(0),
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_reset(0), _res0(0), _res1(0), _raz(0), _rao(0) {}
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uint64_t reset() const { return _reset; }
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uint64_t res0() const { return _res0; }
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uint64_t res1() const { return _res1; }
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uint64_t raz() const { return _raz; }
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uint64_t rao() const { return _rao; }
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// raz/rao implies writes ignored
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uint64_t wi() const { return _raz | _rao; }
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};
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/** Metadata table accessible via the value of the register */
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static std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
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class MiscRegLUTEntryInitializer
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{
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struct MiscRegLUTEntry &entry;
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std::bitset<NUM_MISCREG_INFOS> &info;
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typedef const MiscRegLUTEntryInitializer& chain;
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public:
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chain
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mapsTo(uint32_t l, uint32_t u = 0) const
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{
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entry.lower = l;
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entry.upper = u;
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return *this;
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}
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chain
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res0(uint64_t mask) const
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{
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entry._res0 = mask;
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return *this;
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}
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chain
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res1(uint64_t mask) const
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{
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entry._res1 = mask;
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return *this;
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}
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chain
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raz(uint64_t mask) const
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{
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entry._raz = mask;
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return *this;
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}
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chain
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rao(uint64_t mask) const
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{
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entry._rao = mask;
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return *this;
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}
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chain
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implemented(bool v = true) const
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{
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info[MISCREG_IMPLEMENTED] = v;
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return *this;
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}
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chain
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unimplemented() const
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{
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return implemented(false);
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}
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chain
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unverifiable(bool v = true) const
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{
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info[MISCREG_UNVERIFIABLE] = v;
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return *this;
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}
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chain
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warnNotFail(bool v = true) const
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{
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info[MISCREG_WARN_NOT_FAIL] = v;
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return *this;
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}
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chain
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mutex(bool v = true) const
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{
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info[MISCREG_MUTEX] = v;
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return *this;
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}
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chain
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banked(bool v = true) const
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{
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info[MISCREG_BANKED] = v;
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return *this;
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}
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chain
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banked64(bool v = true) const
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{
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info[MISCREG_BANKED64] = v;
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return *this;
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}
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chain
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bankedChild(bool v = true) const
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{
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info[MISCREG_BANKED_CHILD] = v;
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return *this;
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}
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chain
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userNonSecureRead(bool v = true) const
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{
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info[MISCREG_USR_NS_RD] = v;
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return *this;
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}
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chain
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userNonSecureWrite(bool v = true) const
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{
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info[MISCREG_USR_NS_WR] = v;
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return *this;
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}
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chain
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userSecureRead(bool v = true) const
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{
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info[MISCREG_USR_S_RD] = v;
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return *this;
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}
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chain
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userSecureWrite(bool v = true) const
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{
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info[MISCREG_USR_S_WR] = v;
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return *this;
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}
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chain
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user(bool v = true) const
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{
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userNonSecureRead(v);
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userNonSecureWrite(v);
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userSecureRead(v);
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userSecureWrite(v);
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return *this;
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}
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chain
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privNonSecureRead(bool v = true) const
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{
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info[MISCREG_PRI_NS_RD] = v;
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return *this;
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}
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chain
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privNonSecureWrite(bool v = true) const
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{
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info[MISCREG_PRI_NS_WR] = v;
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return *this;
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}
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chain
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privNonSecure(bool v = true) const
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{
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privNonSecureRead(v);
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privNonSecureWrite(v);
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return *this;
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}
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chain
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privSecureRead(bool v = true) const
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{
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info[MISCREG_PRI_S_RD] = v;
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return *this;
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}
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chain
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privSecureWrite(bool v = true) const
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{
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info[MISCREG_PRI_S_WR] = v;
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return *this;
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}
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chain
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privSecure(bool v = true) const
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{
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privSecureRead(v);
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privSecureWrite(v);
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return *this;
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}
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chain
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priv(bool v = true) const
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{
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privSecure(v);
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privNonSecure(v);
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return *this;
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}
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chain
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privRead(bool v = true) const
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{
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privSecureRead(v);
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privNonSecureRead(v);
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return *this;
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}
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chain
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hypE2HSecureRead(bool v = true) const
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{
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info[MISCREG_HYP_E2H_S_RD] = v;
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return *this;
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}
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chain
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hypE2HNonSecureRead(bool v = true) const
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{
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info[MISCREG_HYP_E2H_NS_RD] = v;
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return *this;
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}
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chain
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hypE2HRead(bool v = true) const
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{
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hypE2HSecureRead(v);
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hypE2HNonSecureRead(v);
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return *this;
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}
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chain
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hypE2HSecureWrite(bool v = true) const
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{
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info[MISCREG_HYP_E2H_S_WR] = v;
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return *this;
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}
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chain
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hypE2HNonSecureWrite(bool v = true) const
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{
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info[MISCREG_HYP_E2H_NS_WR] = v;
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return *this;
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}
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chain
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hypE2HWrite(bool v = true) const
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{
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hypE2HSecureWrite(v);
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hypE2HNonSecureWrite(v);
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return *this;
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}
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chain
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hypE2H(bool v = true) const
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{
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hypE2HRead(v);
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hypE2HWrite(v);
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return *this;
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}
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chain
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hypSecureRead(bool v = true) const
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{
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info[MISCREG_HYP_S_RD] = v;
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return *this;
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}
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chain
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hypNonSecureRead(bool v = true) const
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{
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info[MISCREG_HYP_NS_RD] = v;
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return *this;
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}
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chain
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hypRead(bool v = true) const
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{
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hypE2HRead(v);
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hypSecureRead(v);
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hypNonSecureRead(v);
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return *this;
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}
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chain
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hypSecureWrite(bool v = true) const
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{
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info[MISCREG_HYP_S_WR] = v;
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return *this;
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}
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chain
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hypNonSecureWrite(bool v = true) const
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{
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info[MISCREG_HYP_NS_WR] = v;
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return *this;
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}
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chain
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hypWrite(bool v = true) const
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{
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hypE2HWrite(v);
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hypSecureWrite(v);
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hypNonSecureWrite(v);
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return *this;
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}
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chain
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hypSecure(bool v = true) const
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{
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hypE2HSecureRead(v);
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hypE2HSecureWrite(v);
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hypSecureRead(v);
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hypSecureWrite(v);
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return *this;
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}
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chain
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hyp(bool v = true) const
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{
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hypRead(v);
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hypWrite(v);
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return *this;
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}
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chain
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monE2HRead(bool v = true) const
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{
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info[MISCREG_MON_E2H_RD] = v;
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return *this;
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}
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chain
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monE2HWrite(bool v = true) const
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{
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info[MISCREG_MON_E2H_WR] = v;
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return *this;
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}
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chain
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monE2H(bool v = true) const
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{
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monE2HRead(v);
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monE2HWrite(v);
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return *this;
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}
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chain
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monSecureRead(bool v = true) const
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{
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monE2HRead(v);
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info[MISCREG_MON_NS0_RD] = v;
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return *this;
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}
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chain
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monSecureWrite(bool v = true) const
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{
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monE2HWrite(v);
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info[MISCREG_MON_NS0_WR] = v;
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return *this;
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}
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chain
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monNonSecureRead(bool v = true) const
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{
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monE2HRead(v);
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info[MISCREG_MON_NS1_RD] = v;
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return *this;
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}
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chain
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monNonSecureWrite(bool v = true) const
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{
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monE2HWrite(v);
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info[MISCREG_MON_NS1_WR] = v;
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return *this;
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}
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chain
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mon(bool v = true) const
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{
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monSecureRead(v);
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monSecureWrite(v);
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monNonSecureRead(v);
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monNonSecureWrite(v);
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return *this;
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}
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chain
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monSecure(bool v = true) const
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{
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monSecureRead(v);
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monSecureWrite(v);
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return *this;
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}
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chain
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monNonSecure(bool v = true) const
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{
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monNonSecureRead(v);
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monNonSecureWrite(v);
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return *this;
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}
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chain
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allPrivileges(bool v = true) const
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{
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userNonSecureRead(v);
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userNonSecureWrite(v);
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userSecureRead(v);
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userSecureWrite(v);
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privNonSecureRead(v);
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privNonSecureWrite(v);
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privSecureRead(v);
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privSecureWrite(v);
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hypRead(v);
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hypWrite(v);
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monSecureRead(v);
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monSecureWrite(v);
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monNonSecureRead(v);
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monNonSecureWrite(v);
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return *this;
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}
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chain
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nonSecure(bool v = true) const
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{
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userNonSecureRead(v);
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userNonSecureWrite(v);
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privNonSecureRead(v);
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privNonSecureWrite(v);
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hypRead(v);
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hypWrite(v);
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monNonSecureRead(v);
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monNonSecureWrite(v);
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return *this;
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}
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chain
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secure(bool v = true) const
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{
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userSecureRead(v);
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userSecureWrite(v);
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privSecureRead(v);
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privSecureWrite(v);
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monSecureRead(v);
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monSecureWrite(v);
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return *this;
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}
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chain
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reads(bool v) const
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{
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userNonSecureRead(v);
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userSecureRead(v);
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privNonSecureRead(v);
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privSecureRead(v);
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hypRead(v);
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monSecureRead(v);
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monNonSecureRead(v);
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return *this;
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}
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chain
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writes(bool v) const
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{
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userNonSecureWrite(v);
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userSecureWrite(v);
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privNonSecureWrite(v);
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privSecureWrite(v);
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hypWrite(v);
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monSecureWrite(v);
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monNonSecureWrite(v);
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return *this;
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}
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chain
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|
exceptUserMode() const
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|
{
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user(0);
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return *this;
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}
|
|
chain highest(ArmSystem *const sys) const;
|
|
MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e,
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std::bitset<NUM_MISCREG_INFOS> &i)
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|
: entry(e),
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info(i)
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{
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// force unimplemented registers to be thusly declared
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implemented(1);
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}
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|
};
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|
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const MiscRegLUTEntryInitializer
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InitReg(uint32_t reg)
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{
|
|
return MiscRegLUTEntryInitializer(lookUpMiscReg[reg],
|
|
miscRegInfo[reg]);
|
|
}
|
|
|
|
void initializeMiscRegMetadata();
|
|
|
|
RegVal miscRegs[NUM_MISCREGS];
|
|
const IntRegIndex *intRegMap;
|
|
|
|
void
|
|
updateRegMap(CPSR cpsr)
|
|
{
|
|
if (cpsr.width == 0) {
|
|
intRegMap = IntReg64Map;
|
|
} else {
|
|
switch (cpsr.mode) {
|
|
case MODE_USER:
|
|
case MODE_SYSTEM:
|
|
intRegMap = IntRegUsrMap;
|
|
break;
|
|
case MODE_FIQ:
|
|
intRegMap = IntRegFiqMap;
|
|
break;
|
|
case MODE_IRQ:
|
|
intRegMap = IntRegIrqMap;
|
|
break;
|
|
case MODE_SVC:
|
|
intRegMap = IntRegSvcMap;
|
|
break;
|
|
case MODE_MON:
|
|
intRegMap = IntRegMonMap;
|
|
break;
|
|
case MODE_ABORT:
|
|
intRegMap = IntRegAbtMap;
|
|
break;
|
|
case MODE_HYP:
|
|
intRegMap = IntRegHypMap;
|
|
break;
|
|
case MODE_UNDEFINED:
|
|
intRegMap = IntRegUndMap;
|
|
break;
|
|
default:
|
|
panic("Unrecognized mode setting in CPSR.\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
BaseISADevice &getGenericTimer();
|
|
BaseISADevice &getGICv3CPUInterface();
|
|
|
|
public:
|
|
void clear();
|
|
|
|
protected:
|
|
void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst);
|
|
void clear64(const ArmISAParams &p);
|
|
void initID32(const ArmISAParams &p);
|
|
void initID64(const ArmISAParams &p);
|
|
|
|
void addressTranslation(MMU::ArmTranslationType tran_type,
|
|
BaseMMU::Mode mode, Request::Flags flags, RegVal val);
|
|
void addressTranslation64(MMU::ArmTranslationType tran_type,
|
|
BaseMMU::Mode mode, Request::Flags flags, RegVal val);
|
|
|
|
public:
|
|
SelfDebug*
|
|
getSelfDebug() const
|
|
{
|
|
return selfDebug;
|
|
}
|
|
|
|
static SelfDebug*
|
|
getSelfDebug(ThreadContext *tc)
|
|
{
|
|
auto *arm_isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
|
|
return arm_isa->getSelfDebug();
|
|
}
|
|
|
|
const ArmRelease* getRelease() const { return release; }
|
|
|
|
RegVal readMiscRegNoEffect(int misc_reg) const;
|
|
RegVal readMiscReg(int misc_reg);
|
|
void setMiscRegNoEffect(int misc_reg, RegVal val);
|
|
void setMiscReg(int misc_reg, RegVal val);
|
|
|
|
RegId
|
|
flattenRegId(const RegId& regId) const
|
|
{
|
|
switch (regId.classValue()) {
|
|
case IntRegClass:
|
|
return RegId(IntRegClass, flattenIntIndex(regId.index()));
|
|
case FloatRegClass:
|
|
return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
|
|
case VecRegClass:
|
|
return RegId(VecRegClass, flattenVecIndex(regId.index()));
|
|
case VecElemClass:
|
|
return RegId(VecElemClass, flattenVecElemIndex(regId.index()));
|
|
case VecPredRegClass:
|
|
return RegId(VecPredRegClass,
|
|
flattenVecPredIndex(regId.index()));
|
|
case CCRegClass:
|
|
return RegId(CCRegClass, flattenCCIndex(regId.index()));
|
|
case MiscRegClass:
|
|
return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
|
|
case InvalidRegClass:
|
|
return RegId();
|
|
}
|
|
panic("Unrecognized register class %d.", regId.classValue());
|
|
}
|
|
|
|
int
|
|
flattenIntIndex(int reg) const
|
|
{
|
|
assert(reg >= 0);
|
|
if (reg < NUM_ARCH_INTREGS) {
|
|
return intRegMap[reg];
|
|
} else if (reg < NUM_INTREGS) {
|
|
return reg;
|
|
} else if (reg == INTREG_SPX) {
|
|
CPSR cpsr = miscRegs[MISCREG_CPSR];
|
|
ExceptionLevel el = opModeToEL(
|
|
(OperatingMode) (uint8_t) cpsr.mode);
|
|
if (!cpsr.sp && el != EL0)
|
|
return INTREG_SP0;
|
|
switch (el) {
|
|
case EL3:
|
|
return INTREG_SP3;
|
|
case EL2:
|
|
return INTREG_SP2;
|
|
case EL1:
|
|
return INTREG_SP1;
|
|
case EL0:
|
|
return INTREG_SP0;
|
|
default:
|
|
panic("Invalid exception level");
|
|
return 0; // Never happens.
|
|
}
|
|
} else {
|
|
return flattenIntRegModeIndex(reg);
|
|
}
|
|
}
|
|
|
|
int
|
|
flattenFloatIndex(int reg) const
|
|
{
|
|
assert(reg >= 0);
|
|
return reg;
|
|
}
|
|
|
|
int
|
|
flattenVecIndex(int reg) const
|
|
{
|
|
assert(reg >= 0);
|
|
return reg;
|
|
}
|
|
|
|
int
|
|
flattenVecElemIndex(int reg) const
|
|
{
|
|
assert(reg >= 0);
|
|
return reg;
|
|
}
|
|
|
|
int
|
|
flattenVecPredIndex(int reg) const
|
|
{
|
|
assert(reg >= 0);
|
|
return reg;
|
|
}
|
|
|
|
int
|
|
flattenCCIndex(int reg) const
|
|
{
|
|
assert(reg >= 0);
|
|
return reg;
|
|
}
|
|
|
|
int
|
|
flattenMiscIndex(int reg) const
|
|
{
|
|
assert(reg >= 0);
|
|
int flat_idx = reg;
|
|
|
|
if (reg == MISCREG_SPSR) {
|
|
CPSR cpsr = miscRegs[MISCREG_CPSR];
|
|
switch (cpsr.mode) {
|
|
case MODE_EL0T:
|
|
warn("User mode does not have SPSR\n");
|
|
flat_idx = MISCREG_SPSR;
|
|
break;
|
|
case MODE_EL1T:
|
|
case MODE_EL1H:
|
|
flat_idx = MISCREG_SPSR_EL1;
|
|
break;
|
|
case MODE_EL2T:
|
|
case MODE_EL2H:
|
|
flat_idx = MISCREG_SPSR_EL2;
|
|
break;
|
|
case MODE_EL3T:
|
|
case MODE_EL3H:
|
|
flat_idx = MISCREG_SPSR_EL3;
|
|
break;
|
|
case MODE_USER:
|
|
warn("User mode does not have SPSR\n");
|
|
flat_idx = MISCREG_SPSR;
|
|
break;
|
|
case MODE_FIQ:
|
|
flat_idx = MISCREG_SPSR_FIQ;
|
|
break;
|
|
case MODE_IRQ:
|
|
flat_idx = MISCREG_SPSR_IRQ;
|
|
break;
|
|
case MODE_SVC:
|
|
flat_idx = MISCREG_SPSR_SVC;
|
|
break;
|
|
case MODE_MON:
|
|
flat_idx = MISCREG_SPSR_MON;
|
|
break;
|
|
case MODE_ABORT:
|
|
flat_idx = MISCREG_SPSR_ABT;
|
|
break;
|
|
case MODE_HYP:
|
|
flat_idx = MISCREG_SPSR_HYP;
|
|
break;
|
|
case MODE_UNDEFINED:
|
|
flat_idx = MISCREG_SPSR_UND;
|
|
break;
|
|
default:
|
|
warn("Trying to access SPSR in an invalid mode: %d\n",
|
|
cpsr.mode);
|
|
flat_idx = MISCREG_SPSR;
|
|
break;
|
|
}
|
|
} else if (miscRegInfo[reg][MISCREG_MUTEX]) {
|
|
// Mutually exclusive CP15 register
|
|
switch (reg) {
|
|
case MISCREG_PRRR_MAIR0:
|
|
case MISCREG_PRRR_MAIR0_NS:
|
|
case MISCREG_PRRR_MAIR0_S:
|
|
{
|
|
TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
|
|
// If the muxed reg has been flattened, work out the
|
|
// offset and apply it to the unmuxed reg
|
|
int idxOffset = reg - MISCREG_PRRR_MAIR0;
|
|
if (ttbcr.eae)
|
|
flat_idx = flattenMiscIndex(MISCREG_MAIR0 +
|
|
idxOffset);
|
|
else
|
|
flat_idx = flattenMiscIndex(MISCREG_PRRR +
|
|
idxOffset);
|
|
}
|
|
break;
|
|
case MISCREG_NMRR_MAIR1:
|
|
case MISCREG_NMRR_MAIR1_NS:
|
|
case MISCREG_NMRR_MAIR1_S:
|
|
{
|
|
TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
|
|
// If the muxed reg has been flattened, work out the
|
|
// offset and apply it to the unmuxed reg
|
|
int idxOffset = reg - MISCREG_NMRR_MAIR1;
|
|
if (ttbcr.eae)
|
|
flat_idx = flattenMiscIndex(MISCREG_MAIR1 +
|
|
idxOffset);
|
|
else
|
|
flat_idx = flattenMiscIndex(MISCREG_NMRR +
|
|
idxOffset);
|
|
}
|
|
break;
|
|
case MISCREG_PMXEVTYPER_PMCCFILTR:
|
|
{
|
|
PMSELR pmselr = miscRegs[MISCREG_PMSELR];
|
|
if (pmselr.sel == 31)
|
|
flat_idx = flattenMiscIndex(MISCREG_PMCCFILTR);
|
|
else
|
|
flat_idx = flattenMiscIndex(MISCREG_PMXEVTYPER);
|
|
}
|
|
break;
|
|
default:
|
|
panic("Unrecognized misc. register.\n");
|
|
break;
|
|
}
|
|
} else {
|
|
if (miscRegInfo[reg][MISCREG_BANKED]) {
|
|
bool secure_reg = !highestELIs64 && inSecureState();
|
|
flat_idx += secure_reg ? 2 : 1;
|
|
} else {
|
|
flat_idx = snsBankedIndex64((MiscRegIndex)reg,
|
|
!inSecureState());
|
|
}
|
|
}
|
|
return flat_idx;
|
|
}
|
|
|
|
/**
|
|
* Returns the enconcing equivalent when VHE is implemented and
|
|
* HCR_EL2.E2H is enabled and executing at EL2
|
|
*/
|
|
int
|
|
redirectRegVHE(int misc_reg)
|
|
{
|
|
const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
|
|
if (hcr.e2h == 0x0 || currEL() != EL2)
|
|
return misc_reg;
|
|
SCR scr = readMiscRegNoEffect(MISCREG_SCR_EL3);
|
|
bool sec_el2 = scr.eel2 && release->has(ArmExtension::FEAT_SEL2);
|
|
switch(misc_reg) {
|
|
case MISCREG_SPSR_EL1:
|
|
return MISCREG_SPSR_EL2;
|
|
case MISCREG_ELR_EL1:
|
|
return MISCREG_ELR_EL2;
|
|
case MISCREG_SCTLR_EL1:
|
|
return MISCREG_SCTLR_EL2;
|
|
case MISCREG_CPACR_EL1:
|
|
return MISCREG_CPTR_EL2;
|
|
// case :
|
|
// return MISCREG_TRFCR_EL2;
|
|
case MISCREG_TTBR0_EL1:
|
|
return MISCREG_TTBR0_EL2;
|
|
case MISCREG_TTBR1_EL1:
|
|
return MISCREG_TTBR1_EL2;
|
|
case MISCREG_TCR_EL1:
|
|
return MISCREG_TCR_EL2;
|
|
case MISCREG_AFSR0_EL1:
|
|
return MISCREG_AFSR0_EL2;
|
|
case MISCREG_AFSR1_EL1:
|
|
return MISCREG_AFSR1_EL2;
|
|
case MISCREG_ESR_EL1:
|
|
return MISCREG_ESR_EL2;
|
|
case MISCREG_FAR_EL1:
|
|
return MISCREG_FAR_EL2;
|
|
case MISCREG_MAIR_EL1:
|
|
return MISCREG_MAIR_EL2;
|
|
case MISCREG_AMAIR_EL1:
|
|
return MISCREG_AMAIR_EL2;
|
|
case MISCREG_VBAR_EL1:
|
|
return MISCREG_VBAR_EL2;
|
|
case MISCREG_CONTEXTIDR_EL1:
|
|
return MISCREG_CONTEXTIDR_EL2;
|
|
case MISCREG_CNTKCTL_EL1:
|
|
return MISCREG_CNTHCTL_EL2;
|
|
case MISCREG_CNTP_TVAL_EL0:
|
|
return sec_el2? MISCREG_CNTHPS_TVAL_EL2:
|
|
MISCREG_CNTHP_TVAL_EL2;
|
|
case MISCREG_CNTP_CTL_EL0:
|
|
return sec_el2? MISCREG_CNTHPS_CTL_EL2:
|
|
MISCREG_CNTHP_CTL_EL2;
|
|
case MISCREG_CNTP_CVAL_EL0:
|
|
return sec_el2? MISCREG_CNTHPS_CVAL_EL2:
|
|
MISCREG_CNTHP_CVAL_EL2;
|
|
case MISCREG_CNTV_TVAL_EL0:
|
|
return sec_el2? MISCREG_CNTHVS_TVAL_EL2:
|
|
MISCREG_CNTHV_TVAL_EL2;
|
|
case MISCREG_CNTV_CTL_EL0:
|
|
return sec_el2? MISCREG_CNTHVS_CTL_EL2:
|
|
MISCREG_CNTHV_CTL_EL2;
|
|
case MISCREG_CNTV_CVAL_EL0:
|
|
return sec_el2? MISCREG_CNTHVS_CVAL_EL2:
|
|
MISCREG_CNTHV_CVAL_EL2;
|
|
default:
|
|
return misc_reg;
|
|
}
|
|
/*should not be accessible */
|
|
return misc_reg;
|
|
}
|
|
|
|
int
|
|
snsBankedIndex64(MiscRegIndex reg, bool ns) const
|
|
{
|
|
int reg_as_int = static_cast<int>(reg);
|
|
if (miscRegInfo[reg][MISCREG_BANKED64]) {
|
|
reg_as_int += (release->has(ArmExtension::SECURITY) && !ns) ?
|
|
2 : 1;
|
|
}
|
|
return reg_as_int;
|
|
}
|
|
|
|
std::pair<int,int>
|
|
getMiscIndices(int misc_reg) const
|
|
{
|
|
// Note: indexes of AArch64 registers are left unchanged
|
|
int flat_idx = flattenMiscIndex(misc_reg);
|
|
|
|
if (lookUpMiscReg[flat_idx].lower == 0) {
|
|
return std::make_pair(flat_idx, 0);
|
|
}
|
|
|
|
// do additional S/NS flattenings if mapped to NS while in S
|
|
bool S = !highestELIs64 && inSecureState();
|
|
|
|
int lower = lookUpMiscReg[flat_idx].lower;
|
|
int upper = lookUpMiscReg[flat_idx].upper;
|
|
// upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op)
|
|
lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD];
|
|
upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD];
|
|
return std::make_pair(lower, upper);
|
|
}
|
|
|
|
/** Return true if the PE is in Secure state */
|
|
bool inSecureState() const;
|
|
|
|
/**
|
|
* Returns the current Exception Level (EL) of the ISA object
|
|
*/
|
|
ExceptionLevel currEL() const;
|
|
|
|
unsigned getCurSveVecLenInBits() const;
|
|
|
|
unsigned getCurSveVecLenInBitsAtReset() const { return sveVL * 128; }
|
|
|
|
template <typename Elem>
|
|
static void
|
|
zeroSveVecRegUpperPart(Elem *v, unsigned eCount)
|
|
{
|
|
static_assert(sizeof(Elem) <= sizeof(uint64_t),
|
|
"Elem type is too large.");
|
|
eCount *= (sizeof(uint64_t) / sizeof(Elem));
|
|
for (int i = 16 / sizeof(Elem); i < eCount; ++i) {
|
|
v[i] = 0;
|
|
}
|
|
}
|
|
|
|
void serialize(CheckpointOut &cp) const override;
|
|
void unserialize(CheckpointIn &cp) override;
|
|
|
|
void startup() override;
|
|
|
|
void setupThreadContext();
|
|
|
|
PCStateBase *
|
|
newPCState(Addr new_inst_addr=0) const override
|
|
{
|
|
return new PCState(new_inst_addr);
|
|
}
|
|
|
|
void takeOverFrom(ThreadContext *new_tc,
|
|
ThreadContext *old_tc) override;
|
|
|
|
enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; }
|
|
|
|
/** Returns true if the ISA has a GICv3 cpu interface */
|
|
bool
|
|
haveGICv3CpuIfc() const
|
|
{
|
|
// gicv3CpuInterface is initialized at startup time, hence
|
|
// trying to read its value before the startup stage will lead
|
|
// to an error
|
|
assert(afterStartup);
|
|
return gicv3CpuInterface != nullptr;
|
|
}
|
|
|
|
PARAMS(ArmISA);
|
|
|
|
ISA(const Params &p);
|
|
|
|
uint64_t
|
|
getExecutingAsid() const override
|
|
{
|
|
return readMiscRegNoEffect(MISCREG_CONTEXTIDR);
|
|
}
|
|
|
|
bool
|
|
inUserMode() const override
|
|
{
|
|
CPSR cpsr = miscRegs[MISCREG_CPSR];
|
|
return ArmISA::inUserMode(cpsr);
|
|
}
|
|
|
|
void copyRegsFrom(ThreadContext *src) override;
|
|
|
|
void handleLockedRead(const RequestPtr &req) override;
|
|
void handleLockedRead(ExecContext *xc, const RequestPtr &req) override;
|
|
|
|
bool handleLockedWrite(const RequestPtr &req,
|
|
Addr cacheBlockMask) override;
|
|
bool handleLockedWrite(ExecContext *xc, const RequestPtr &req,
|
|
Addr cacheBlockMask) override;
|
|
|
|
void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override;
|
|
void handleLockedSnoop(ExecContext *xc, PacketPtr pkt,
|
|
Addr cacheBlockMask) override;
|
|
void handleLockedSnoopHit() override;
|
|
void handleLockedSnoopHit(ExecContext *xc) override;
|
|
|
|
void globalClearExclusive() override;
|
|
void globalClearExclusive(ExecContext *xc) override;
|
|
};
|
|
|
|
} // namespace ArmISA
|
|
} // namespace gem5
|
|
|
|
#endif
|