Gabe Black 0167f66c13 mips: Explicitly truncate the syscall return value down to 32 bits. ...

The IntReg type is 32 bits, and using it to cast the syscall return
value is appropriate, but we're attempting to get rid of the ISA
specific register types.

Change-Id: I42496dd2cc086a6b718e1ce087fef81bb897d02f
Reviewed-on: https://gem5-review.googlesource.com/c/13619
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

2018-11-06 00:35:20 +00:00

..

alpha

arch: Get rid of the unused type AnyReg.

2018-10-17 20:15:26 +00:00

arm

arch, arm: Return s1Req upon fault in s2Lookup

2018-11-05 09:56:37 +00:00

generic

arch: Include some additional headers in arch/generic/mmapped_ipr.cc.

2018-10-17 20:19:03 +00:00

hsail

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

mips

mips: Explicitly truncate the syscall return value down to 32 bits.

2018-11-06 00:35:20 +00:00

null

null: Claim to use 64 bit floating point registers.

2018-11-05 23:43:10 +00:00

power

arch: Get rid of the unused type AnyReg.

2018-10-17 20:15:26 +00:00

riscv

syscall_emul: expand AuxVector class

2018-09-19 20:51:17 +00:00

sparc

sparc: Switch the FloatReg and FloatRegBits types to be 64 bit.

2018-11-05 23:42:51 +00:00

x86

arch: Get rid of the unused type AnyReg.

2018-10-17 20:15:26 +00:00

isa_parser.py

arch, arm: Fix implicit-fallthrough GCC warnings

2018-03-20 20:17:00 +00:00

micro_asm_test.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

micro_asm.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

SConscript

arch: Remove the "arch/tlb.hh" switching header.

2018-01-23 20:39:24 +00:00