00df9016fe
--HG-- rename : src/dev/SimConsole.py => src/dev/Terminal.py rename : src/dev/simconsole.cc => src/dev/terminal.cc rename : src/dev/simconsole.hh => src/dev/terminal.hh
298 lines
9.6 KiB
C++
Executable File
298 lines
9.6 KiB
C++
Executable File
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Ali Saidi
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* Steve Reinhardt
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* Erik Hallnor
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*/
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/** @file
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* Mips Console Definition
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*/
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#include <cstddef>
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#include <string>
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#include "arch/mips/system.hh"
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#include "base/inifile.hh"
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#include "base/str.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "dev/mips/console.hh"
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#include "dev/platform.hh"
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#include "dev/simple_disk.hh"
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#include "dev/terminal.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "mem/physical.hh"
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#include "params/MipsConsole.hh"
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#include "sim/sim_object.hh"
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using namespace std;
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using namespace MipsISA;
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MipsConsole::MipsConsole(const Params *p)
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: BasicPioDevice(p), disk(p->disk), terminal(p->terminal),
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system(p->system), cpu(p->cpu)
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{
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pioSize = sizeof(struct MipsAccess);
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mipsAccess = new Access();
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mipsAccess->last_offset = pioSize - 1;
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mipsAccess->version = MIPS_ACCESS_VERSION;
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mipsAccess->diskUnit = 1;
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mipsAccess->diskCount = 0;
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mipsAccess->diskPAddr = 0;
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mipsAccess->diskBlock = 0;
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mipsAccess->diskOperation = 0;
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mipsAccess->outputChar = 0;
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mipsAccess->inputChar = 0;
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bzero(mipsAccess->cpuStack, sizeof(mipsAccess->cpuStack));
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}
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void
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MipsConsole::startup()
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{
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system->setMipsAccess(pioAddr);
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mipsAccess->numCPUs = system->getNumCPUs();
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mipsAccess->kernStart = MipsISA::Phys2K0Seg(system->getKernelStart());
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mipsAccess->kernEnd = MipsISA::Phys2K0Seg(system->getKernelEnd());
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mipsAccess->entryPoint = MipsISA::Phys2K0Seg(system->getKernelEntry());
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mipsAccess->mem_size = system->physmem->size();
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mipsAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
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mipsAccess->intrClockFrequency = params()->platform->intrFrequency();
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}
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Tick
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MipsConsole::read(PacketPtr pkt)
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{
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/** XXX Do we want to push the addr munging to a bus brige or something? So
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* the device has it's physical address and then the bridge adds on whatever
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* machine dependent address swizzle is required?
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*/
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = pkt->getAddr() - pioAddr;
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pkt->allocate();
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switch (pkt->getSize())
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{
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case sizeof(uint32_t):
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switch (daddr)
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{
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case offsetof(MipsAccess, last_offset):
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pkt->set(mipsAccess->last_offset);
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break;
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case offsetof(MipsAccess, version):
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pkt->set(mipsAccess->version);
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break;
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case offsetof(MipsAccess, numCPUs):
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pkt->set(mipsAccess->numCPUs);
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break;
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case offsetof(MipsAccess, intrClockFrequency):
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pkt->set(mipsAccess->intrClockFrequency);
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break;
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case offsetof(MipsAccess, inputChar):
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pkt->set(terminal->console_in());
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break;
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case offsetof(MipsAccess, cpuClock):
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pkt->set(mipsAccess->cpuClock);
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break;
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case offsetof(MipsAccess, mem_size):
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pkt->set(mipsAccess->mem_size);
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break;
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case offsetof(MipsAccess, kernStart):
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pkt->set(mipsAccess->kernStart);
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break;
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case offsetof(MipsAccess, kernEnd):
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pkt->set(mipsAccess->kernEnd);
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break;
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case offsetof(MipsAccess, entryPoint):
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pkt->set(mipsAccess->entryPoint);
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break;
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case offsetof(MipsAccess, diskUnit):
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pkt->set(mipsAccess->diskUnit);
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break;
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case offsetof(MipsAccess, diskCount):
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pkt->set(mipsAccess->diskCount);
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break;
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case offsetof(MipsAccess, diskPAddr):
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pkt->set(mipsAccess->diskPAddr);
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break;
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case offsetof(MipsAccess, diskBlock):
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pkt->set(mipsAccess->diskBlock);
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break;
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case offsetof(MipsAccess, diskOperation):
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pkt->set(mipsAccess->diskOperation);
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break;
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case offsetof(MipsAccess, outputChar):
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pkt->set(mipsAccess->outputChar);
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break;
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default:
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int cpunum = (daddr - offsetof(MipsAccess, cpuStack)) /
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sizeof(mipsAccess->cpuStack[0]);
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if (cpunum >= 0 && cpunum < 64)
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pkt->set(mipsAccess->cpuStack[cpunum]);
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else
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panic("Unknown 32bit access, %#x\n", daddr);
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}
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//DPRINTF(MipsConsole, "read: offset=%#x val=%#x\n", daddr,
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// pkt->get<uint64_t>());
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break;
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default:
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pkt->setBadAddress();
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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Tick
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MipsConsole::write(PacketPtr pkt)
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{
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = pkt->getAddr() - pioAddr;
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uint32_t val = pkt->get<uint32_t>();
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assert(pkt->getSize() == sizeof(uint32_t));
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switch (daddr) {
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case offsetof(MipsAccess, diskUnit):
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mipsAccess->diskUnit = val;
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break;
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case offsetof(MipsAccess, diskCount):
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mipsAccess->diskCount = val;
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break;
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case offsetof(MipsAccess, diskPAddr):
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mipsAccess->diskPAddr = val;
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break;
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case offsetof(MipsAccess, diskBlock):
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mipsAccess->diskBlock = val;
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break;
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case offsetof(MipsAccess, diskOperation):
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if (val == 0x13)
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disk->read(mipsAccess->diskPAddr, mipsAccess->diskBlock,
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mipsAccess->diskCount);
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else
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panic("Invalid disk operation!");
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break;
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case offsetof(MipsAccess, outputChar):
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terminal->out((char)(val & 0xff));
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break;
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default:
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int cpunum = (daddr - offsetof(MipsAccess, cpuStack)) /
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sizeof(mipsAccess->cpuStack[0]);
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warn("%d: Trying to launch CPU number %d!", curTick, cpunum);
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assert(val > 0 && "Must not access primary cpu");
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if (cpunum >= 0 && cpunum < 64)
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mipsAccess->cpuStack[cpunum] = val;
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else
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panic("Unknown 32bit access, %#x\n", daddr);
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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void
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MipsConsole::Access::serialize(ostream &os)
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{
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SERIALIZE_SCALAR(last_offset);
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SERIALIZE_SCALAR(version);
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SERIALIZE_SCALAR(numCPUs);
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SERIALIZE_SCALAR(mem_size);
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SERIALIZE_SCALAR(cpuClock);
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SERIALIZE_SCALAR(intrClockFrequency);
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SERIALIZE_SCALAR(kernStart);
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SERIALIZE_SCALAR(kernEnd);
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SERIALIZE_SCALAR(entryPoint);
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SERIALIZE_SCALAR(diskUnit);
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SERIALIZE_SCALAR(diskCount);
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SERIALIZE_SCALAR(diskPAddr);
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SERIALIZE_SCALAR(diskBlock);
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SERIALIZE_SCALAR(diskOperation);
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SERIALIZE_SCALAR(outputChar);
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SERIALIZE_SCALAR(inputChar);
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SERIALIZE_ARRAY(cpuStack,64);
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}
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void
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MipsConsole::Access::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(last_offset);
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UNSERIALIZE_SCALAR(version);
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UNSERIALIZE_SCALAR(numCPUs);
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UNSERIALIZE_SCALAR(mem_size);
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UNSERIALIZE_SCALAR(cpuClock);
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UNSERIALIZE_SCALAR(intrClockFrequency);
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UNSERIALIZE_SCALAR(kernStart);
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UNSERIALIZE_SCALAR(kernEnd);
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UNSERIALIZE_SCALAR(entryPoint);
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UNSERIALIZE_SCALAR(diskUnit);
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UNSERIALIZE_SCALAR(diskCount);
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UNSERIALIZE_SCALAR(diskPAddr);
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UNSERIALIZE_SCALAR(diskBlock);
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UNSERIALIZE_SCALAR(diskOperation);
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UNSERIALIZE_SCALAR(outputChar);
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UNSERIALIZE_SCALAR(inputChar);
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UNSERIALIZE_ARRAY(cpuStack, 64);
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}
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void
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MipsConsole::serialize(ostream &os)
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{
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mipsAccess->serialize(os);
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}
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void
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MipsConsole::unserialize(Checkpoint *cp, const std::string §ion)
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{
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mipsAccess->unserialize(cp, section);
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}
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MipsConsole *
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MipsConsoleParams::create()
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{
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return new MipsConsole(this);
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}
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