00da089029
This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
461 lines
16 KiB
C++
461 lines
16 KiB
C++
/*
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* Copyright (c) 2010, 2012-2016 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_ISA_HH__
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#define __ARCH_ARM_ISA_HH__
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#include "arch/arm/isa_device.hh"
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#include "arch/arm/registers.hh"
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#include "arch/arm/system.hh"
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#include "arch/arm/tlb.hh"
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#include "arch/arm/types.hh"
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#include "arch/generic/traits.hh"
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#include "debug/Checkpoint.hh"
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#include "enums/VecRegRenameMode.hh"
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#include "sim/sim_object.hh"
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#include "enums/DecoderFlavour.hh"
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struct ArmISAParams;
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struct DummyArmISADeviceParams;
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class ThreadContext;
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class Checkpoint;
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class EventManager;
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namespace ArmISA
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{
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class ISA : public SimObject
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{
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protected:
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// Parent system
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ArmSystem *system;
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// Micro Architecture
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const Enums::DecoderFlavour _decoderFlavour;
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const Enums::VecRegRenameMode _vecRegRenameMode;
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/** Dummy device for to handle non-existing ISA devices */
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DummyISADevice dummyDevice;
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// PMU belonging to this ISA
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BaseISADevice *pmu;
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// Generic timer interface belonging to this ISA
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std::unique_ptr<BaseISADevice> timer;
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// Cached copies of system-level properties
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bool highestELIs64;
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bool haveSecurity;
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bool haveLPAE;
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bool haveVirtualization;
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bool haveLargeAsid64;
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uint8_t physAddrRange64;
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/** Register translation entry used in lookUpMiscReg */
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struct MiscRegLUTEntry {
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uint32_t lower;
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uint32_t upper;
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};
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struct MiscRegInitializerEntry {
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uint32_t index;
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struct MiscRegLUTEntry entry;
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};
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/** Register table noting all translations */
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static const struct MiscRegInitializerEntry MiscRegSwitch[];
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/** Translation table accessible via the value of the register */
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std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
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MiscReg miscRegs[NumMiscRegs];
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const IntRegIndex *intRegMap;
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void
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updateRegMap(CPSR cpsr)
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{
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if (cpsr.width == 0) {
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intRegMap = IntReg64Map;
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} else {
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switch (cpsr.mode) {
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case MODE_USER:
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case MODE_SYSTEM:
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intRegMap = IntRegUsrMap;
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break;
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case MODE_FIQ:
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intRegMap = IntRegFiqMap;
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break;
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case MODE_IRQ:
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intRegMap = IntRegIrqMap;
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break;
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case MODE_SVC:
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intRegMap = IntRegSvcMap;
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break;
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case MODE_MON:
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intRegMap = IntRegMonMap;
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break;
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case MODE_ABORT:
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intRegMap = IntRegAbtMap;
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break;
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case MODE_HYP:
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intRegMap = IntRegHypMap;
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break;
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case MODE_UNDEFINED:
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intRegMap = IntRegUndMap;
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break;
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default:
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panic("Unrecognized mode setting in CPSR.\n");
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}
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}
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}
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BaseISADevice &getGenericTimer(ThreadContext *tc);
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private:
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inline void assert32(ThreadContext *tc) {
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CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
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assert(cpsr.width);
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}
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inline void assert64(ThreadContext *tc) {
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CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
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assert(!cpsr.width);
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}
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void tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
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bool secure_lookup, uint8_t target_el);
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void tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el);
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void tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el);
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void tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup,
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bool hyp, uint8_t target_el);
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public:
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void clear();
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void clear64(const ArmISAParams *p);
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MiscReg readMiscRegNoEffect(int misc_reg) const;
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MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
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void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
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void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
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RegId
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flattenRegId(const RegId& regId) const
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{
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switch (regId.classValue()) {
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case IntRegClass:
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return RegId(IntRegClass, flattenIntIndex(regId.index()));
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case FloatRegClass:
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return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
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case VecRegClass:
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return RegId(VecRegClass, flattenVecIndex(regId.index()));
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case VecElemClass:
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return RegId(VecElemClass, flattenVecElemIndex(regId.index()));
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case CCRegClass:
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return RegId(CCRegClass, flattenCCIndex(regId.index()));
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case MiscRegClass:
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return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
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}
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return RegId();
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}
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int
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flattenIntIndex(int reg) const
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{
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assert(reg >= 0);
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if (reg < NUM_ARCH_INTREGS) {
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return intRegMap[reg];
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} else if (reg < NUM_INTREGS) {
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return reg;
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} else if (reg == INTREG_SPX) {
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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ExceptionLevel el = opModeToEL(
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(OperatingMode) (uint8_t) cpsr.mode);
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if (!cpsr.sp && el != EL0)
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return INTREG_SP0;
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switch (el) {
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case EL3:
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return INTREG_SP3;
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case EL2:
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return INTREG_SP2;
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case EL1:
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return INTREG_SP1;
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case EL0:
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return INTREG_SP0;
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default:
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panic("Invalid exception level");
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break;
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}
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} else {
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return flattenIntRegModeIndex(reg);
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}
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}
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int
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flattenFloatIndex(int reg) const
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{
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assert(reg >= 0);
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return reg;
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}
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int
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flattenVecIndex(int reg) const
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{
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assert(reg >= 0);
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return reg;
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}
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int
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flattenVecElemIndex(int reg) const
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{
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assert(reg >= 0);
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return reg;
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}
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int
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flattenCCIndex(int reg) const
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{
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assert(reg >= 0);
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return reg;
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}
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int
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flattenMiscIndex(int reg) const
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{
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assert(reg >= 0);
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int flat_idx = reg;
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if (reg == MISCREG_SPSR) {
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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switch (cpsr.mode) {
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case MODE_EL0T:
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warn("User mode does not have SPSR\n");
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flat_idx = MISCREG_SPSR;
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break;
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case MODE_EL1T:
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case MODE_EL1H:
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flat_idx = MISCREG_SPSR_EL1;
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break;
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case MODE_EL2T:
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case MODE_EL2H:
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flat_idx = MISCREG_SPSR_EL2;
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break;
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case MODE_EL3T:
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case MODE_EL3H:
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flat_idx = MISCREG_SPSR_EL3;
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break;
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case MODE_USER:
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warn("User mode does not have SPSR\n");
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flat_idx = MISCREG_SPSR;
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break;
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case MODE_FIQ:
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flat_idx = MISCREG_SPSR_FIQ;
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break;
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case MODE_IRQ:
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flat_idx = MISCREG_SPSR_IRQ;
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break;
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case MODE_SVC:
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flat_idx = MISCREG_SPSR_SVC;
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break;
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case MODE_MON:
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flat_idx = MISCREG_SPSR_MON;
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break;
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case MODE_ABORT:
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flat_idx = MISCREG_SPSR_ABT;
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break;
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case MODE_HYP:
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flat_idx = MISCREG_SPSR_HYP;
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break;
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case MODE_UNDEFINED:
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flat_idx = MISCREG_SPSR_UND;
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break;
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default:
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warn("Trying to access SPSR in an invalid mode: %d\n",
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cpsr.mode);
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flat_idx = MISCREG_SPSR;
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break;
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}
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} else if (miscRegInfo[reg][MISCREG_MUTEX]) {
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// Mutually exclusive CP15 register
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switch (reg) {
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case MISCREG_PRRR_MAIR0:
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case MISCREG_PRRR_MAIR0_NS:
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case MISCREG_PRRR_MAIR0_S:
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{
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TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
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// If the muxed reg has been flattened, work out the
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// offset and apply it to the unmuxed reg
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int idxOffset = reg - MISCREG_PRRR_MAIR0;
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if (ttbcr.eae)
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flat_idx = flattenMiscIndex(MISCREG_MAIR0 +
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idxOffset);
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else
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flat_idx = flattenMiscIndex(MISCREG_PRRR +
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idxOffset);
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}
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break;
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case MISCREG_NMRR_MAIR1:
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case MISCREG_NMRR_MAIR1_NS:
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case MISCREG_NMRR_MAIR1_S:
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{
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TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
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// If the muxed reg has been flattened, work out the
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// offset and apply it to the unmuxed reg
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int idxOffset = reg - MISCREG_NMRR_MAIR1;
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if (ttbcr.eae)
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flat_idx = flattenMiscIndex(MISCREG_MAIR1 +
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idxOffset);
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else
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flat_idx = flattenMiscIndex(MISCREG_NMRR +
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idxOffset);
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}
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break;
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case MISCREG_PMXEVTYPER_PMCCFILTR:
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{
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PMSELR pmselr = miscRegs[MISCREG_PMSELR];
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if (pmselr.sel == 31)
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flat_idx = flattenMiscIndex(MISCREG_PMCCFILTR);
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else
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flat_idx = flattenMiscIndex(MISCREG_PMXEVTYPER);
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}
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break;
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default:
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panic("Unrecognized misc. register.\n");
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break;
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}
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} else {
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if (miscRegInfo[reg][MISCREG_BANKED]) {
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bool secureReg = haveSecurity && !highestELIs64 &&
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inSecureState(miscRegs[MISCREG_SCR],
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miscRegs[MISCREG_CPSR]);
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flat_idx += secureReg ? 2 : 1;
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}
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}
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return flat_idx;
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}
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std::pair<int,int> getMiscIndices(int misc_reg) const
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{
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// Note: indexes of AArch64 registers are left unchanged
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int flat_idx = flattenMiscIndex(misc_reg);
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if (lookUpMiscReg[flat_idx].lower == 0) {
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return std::make_pair(flat_idx, 0);
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}
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// do additional S/NS flattenings if mapped to NS while in S
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bool S = haveSecurity && !highestELIs64 &&
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inSecureState(miscRegs[MISCREG_SCR],
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miscRegs[MISCREG_CPSR]);
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int lower = lookUpMiscReg[flat_idx].lower;
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int upper = lookUpMiscReg[flat_idx].upper;
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// upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op)
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lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD];
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upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD];
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return std::make_pair(lower, upper);
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}
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void serialize(CheckpointOut &cp) const
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{
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DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
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SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
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SERIALIZE_SCALAR(highestELIs64);
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SERIALIZE_SCALAR(haveSecurity);
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SERIALIZE_SCALAR(haveLPAE);
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SERIALIZE_SCALAR(haveVirtualization);
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SERIALIZE_SCALAR(haveLargeAsid64);
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SERIALIZE_SCALAR(physAddrRange64);
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}
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void unserialize(CheckpointIn &cp)
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{
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DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
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UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
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CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
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updateRegMap(tmp_cpsr);
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UNSERIALIZE_SCALAR(highestELIs64);
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UNSERIALIZE_SCALAR(haveSecurity);
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UNSERIALIZE_SCALAR(haveLPAE);
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UNSERIALIZE_SCALAR(haveVirtualization);
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UNSERIALIZE_SCALAR(haveLargeAsid64);
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UNSERIALIZE_SCALAR(physAddrRange64);
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}
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void startup(ThreadContext *tc) {}
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Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
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Enums::VecRegRenameMode
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vecRegRenameMode() const
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{
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return _vecRegRenameMode;
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}
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/// Explicitly import the otherwise hidden startup
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using SimObject::startup;
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typedef ArmISAParams Params;
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const Params *params() const;
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ISA(Params *p);
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};
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}
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template<>
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struct initRenameMode<ArmISA::ISA>
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{
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static Enums::VecRegRenameMode mode(const ArmISA::ISA* isa)
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{
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return isa->vecRegRenameMode();
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}
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static bool equals(const ArmISA::ISA* isa1, const ArmISA::ISA* isa2)
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{
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return mode(isa1) == mode(isa2);
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}
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};
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#endif
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