00da089029
This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
116 lines
3.8 KiB
C++
116 lines
3.8 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ALPHA_REGISTERS_HH__
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#define __ARCH_ALPHA_REGISTERS_HH__
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#include "arch/alpha/generated/max_inst_regs.hh"
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#include "arch/alpha/ipr.hh"
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#include "arch/generic/types.hh"
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#include "arch/generic/vec_reg.hh"
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#include "base/types.hh"
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namespace AlphaISA {
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using AlphaISAInst::MaxInstSrcRegs;
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using AlphaISAInst::MaxInstDestRegs;
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// Locked read/write flags are can't be detected by the ISA parser
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const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
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typedef uint64_t IntReg;
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// floating point register file entry type
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typedef double FloatReg;
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typedef uint64_t FloatRegBits;
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// control register file contents
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typedef uint64_t MiscReg;
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// dummy typedef since we don't have CC regs
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typedef uint8_t CCReg;
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// dummy typedefs since we don't have vector regs
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constexpr unsigned NumVecElemPerVecReg = 2;
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using VecElem = uint32_t;
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using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
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using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
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using VecRegContainer = VecReg::Container;
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// This has to be one to prevent warnings that are treated as errors
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constexpr unsigned NumVecRegs = 1;
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union AnyReg
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{
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IntReg intreg;
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FloatReg fpreg;
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MiscReg ctrlreg;
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};
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enum MiscRegIndex
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{
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MISCREG_FPCR = NumInternalProcRegs,
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MISCREG_UNIQ,
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MISCREG_LOCKFLAG,
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MISCREG_LOCKADDR,
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MISCREG_INTR,
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NUM_MISCREGS
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};
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// semantically meaningful register indices
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const RegIndex ZeroReg = 31; // architecturally meaningful
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// the rest of these depend on the ABI
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const RegIndex StackPointerReg = 30;
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const RegIndex GlobalPointerReg = 29;
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const RegIndex ProcedureValueReg = 27;
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const RegIndex ReturnAddressReg = 26;
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const RegIndex ReturnValueReg = 0;
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const RegIndex FramePointerReg = 15;
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const RegIndex SyscallNumReg = 0;
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const RegIndex FirstArgumentReg = 16;
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const RegIndex SyscallPseudoReturnReg = 20;
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const RegIndex SyscallSuccessReg = 19;
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const int NumIntArchRegs = 32;
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const int NumPALShadowRegs = 8;
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const int NumFloatArchRegs = 32;
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const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
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const int NumFloatRegs = NumFloatArchRegs;
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const int NumCCRegs = 0;
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const int NumMiscRegs = NUM_MISCREGS;
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const int TotalNumRegs =
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NumIntRegs + NumFloatRegs + NumMiscRegs;
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} // namespace AlphaISA
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#endif // __ARCH_ALPHA_REGFILE_HH__
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