d11c40dcac
This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
150 lines
5.2 KiB
Python
150 lines
5.2 KiB
Python
# Copyright (c) 2015, 2023 Arm Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# Basic elastic traces replay script that configures a Trace CPU
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import argparse
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from m5.util import (
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addToPath,
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fatal,
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)
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addToPath("../")
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from common import (
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MemConfig,
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Options,
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Simulation,
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)
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from common.Caches import *
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def config_cache(args, system):
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"""
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Configure the cache hierarchy. Only two configurations are natively
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supported as an example: L1(I/D) only or L1 + L2.
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"""
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from common.CacheConfig import _get_cache_opts
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system.l1i = L1_ICache(**_get_cache_opts("l1i", args))
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system.l1d = L1_DCache(**_get_cache_opts("l1d", args))
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system.cpu.dcache_port = system.l1d.cpu_side
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system.cpu.icache_port = system.l1i.cpu_side
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if args.l2cache:
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# Provide a clock for the L2 and the L1-to-L2 bus here as they
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# are not connected using addTwoLevelCacheHierarchy. Use the
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# same clock as the CPUs.
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system.l2 = L2Cache(
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clk_domain=system.cpu_clk_domain, **_get_cache_opts("l2", args)
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)
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system.tol2bus = L2XBar(clk_domain=system.cpu_clk_domain)
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system.l2.cpu_side = system.tol2bus.mem_side_ports
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system.l2.mem_side = system.membus.cpu_side_ports
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system.l1i.mem_side = system.tol2bus.cpu_side_ports
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system.l1d.mem_side = system.tol2bus.cpu_side_ports
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else:
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system.l1i.mem_side = system.membus.cpu_side_ports
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system.l1d.mem_side = system.membus.cpu_side_ports
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parser = argparse.ArgumentParser()
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Options.addCommonOptions(parser)
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if "--ruby" in sys.argv:
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print(
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"This script does not support Ruby configuration, mainly"
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" because Trace CPU has been tested only with classic memory system"
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)
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sys.exit(1)
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args = parser.parse_args()
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if args.num_cpus > 1:
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fatal("This script does not support multi-processor trace replay.\n")
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system = System(
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mem_mode=TraceCPU.memory_mode(),
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mem_ranges=[AddrRange(args.mem_size)],
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cache_line_size=args.cacheline_size,
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)
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# Generate the TraceCPU
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system.cpu = TraceCPU()
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# Create a top-level voltage domain
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system.voltage_domain = VoltageDomain(voltage=args.sys_voltage)
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# Create a source clock for the system. This is used as the clock period for
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# xbar and memory
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system.clk_domain = SrcClockDomain(
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clock=args.sys_clock, voltage_domain=system.voltage_domain
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)
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# Create a CPU voltage domain
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system.cpu_voltage_domain = VoltageDomain()
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# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
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# is actually used only by the caches connected to the CPU.
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system.cpu_clk_domain = SrcClockDomain(
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clock=args.cpu_clock, voltage_domain=system.cpu_voltage_domain
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)
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# All cpus belong to a common cpu_clk_domain, therefore running at a common
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# frequency.
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for cpu in system.cpu:
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cpu.clk_domain = system.cpu_clk_domain
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# Assign input trace files to the Trace CPU
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system.cpu.instTraceFile = args.inst_trace_file
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system.cpu.dataTraceFile = args.data_trace_file
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# Configure the classic memory system args
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MemClass = Simulation.setMemClass(args)
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system.membus = SystemXBar()
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system.system_port = system.membus.cpu_side_ports
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# Configure the classic cache hierarchy
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config_cache(args, system)
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MemConfig.config_mem(args, system)
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root = Root(full_system=False, system=system)
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Simulation.run(args, root, system, None)
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