f2f86a3e42
This PR changes memory and cache sizes in various parts of the gem5 codebase to use binary units (e.g. KiB) instead of metric units (e.g. kB). This makes the codebase more consistent, as gem5 automatically converts memory and cache sizes that are in metric units to binary units. This PR also adds a warning message to let users know when an auto-conversion from base 10 to base 2 units occurs. There were a few places in configs and in the comments of various files where I didn't change the metric units, as I couldn't figure out where the parameters with those units were being used.
250 lines
8.4 KiB
Python
250 lines
8.4 KiB
Python
# Copyright (c) 2016-2017, 2022-2024 Arm Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""This script is the syscall emulation example script from the ARM
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Research Starter Kit on System Modeling. More information can be found
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at: http://www.arm.com/ResearchEnablement/SystemModeling
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"""
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import argparse
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import os
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import shlex
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import m5
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from m5.objects import *
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from m5.util import addToPath
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m5.util.addToPath("../..")
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import devices
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from common import (
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MemConfig,
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ObjectList,
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)
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from common.cores.arm import (
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HPI,
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O3_ARM_v7a,
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)
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# Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class,
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# l1_icache_class, l1_dcache_class, l2_Cache_class). Any of
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# the cache class may be 'None' if the particular cache is not present.
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cpu_types = {
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"atomic": (AtomicSimpleCPU, None, None, None),
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"minor": (MinorCPU, devices.L1I, devices.L1D, devices.L2),
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"hpi": (HPI.HPI, HPI.HPI_ICache, HPI.HPI_DCache, HPI.HPI_L2),
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"o3": (
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O3_ARM_v7a.O3_ARM_v7a_3,
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O3_ARM_v7a.O3_ARM_v7a_ICache,
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O3_ARM_v7a.O3_ARM_v7a_DCache,
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O3_ARM_v7a.O3_ARM_v7aL2,
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),
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}
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def get_processes(cmd):
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"""Interprets commands to run and returns a list of processes"""
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cwd = os.getcwd()
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multiprocesses = []
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for idx, c in enumerate(cmd):
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argv = shlex.split(c)
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process = Process(pid=100 + idx, cwd=cwd, cmd=argv, executable=argv[0])
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process.gid = os.getgid()
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print("info: %d. command and arguments: %s" % (idx + 1, process.cmd))
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multiprocesses.append(process)
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return multiprocesses
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def create(args):
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"""Create and configure the system object."""
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cpu_class = cpu_types[args.cpu][0]
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mem_mode = cpu_class.memory_mode()
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# Only simulate caches when using a timing CPU (e.g., the HPI model)
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want_caches = True if mem_mode == "timing" else False
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system = devices.SimpleSeSystem(
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mem_mode=mem_mode,
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)
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# Add CPUs to the system. A cluster of CPUs typically have
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# private L1 caches and a shared L2 cache.
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system.cpu_cluster = devices.ArmCpuCluster(
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system,
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args.num_cores,
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args.cpu_freq,
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"1.2V",
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*cpu_types[args.cpu],
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tarmac_gen=args.tarmac_gen,
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tarmac_dest=args.tarmac_dest,
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)
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# Create a cache hierarchy for the cluster. We are assuming that
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# clusters have core-private L1 caches and an L2 that's shared
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# within the cluster.
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system.addCaches(want_caches, last_cache_level=2)
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# Tell components about the expected physical memory ranges. This
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# is, for example, used by the MemConfig helper to determine where
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# to map DRAMs in the physical address space.
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system.mem_ranges = [AddrRange(start=0, size=args.mem_size)]
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# Configure the off-chip memory system.
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MemConfig.config_mem(args, system)
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# Wire up the system's memory system
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system.connect()
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# Parse the command line and get a list of Processes instances
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# that we can pass to gem5.
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processes = get_processes(args.commands_to_run)
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if len(processes) != args.num_cores:
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print(
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"Error: Cannot map %d command(s) onto %d CPU(s)"
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% (len(processes), args.num_cores)
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)
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sys.exit(1)
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system.workload = SEWorkload.init_compatible(processes[0].executable)
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# Assign one workload to each CPU
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for cpu, workload in zip(system.cpu_cluster.cpus, processes):
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cpu.workload = workload
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return system
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def main():
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parser = argparse.ArgumentParser(epilog=__doc__)
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parser.add_argument(
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"commands_to_run",
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metavar="command(s)",
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nargs="*",
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help="Command(s) to run",
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)
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parser.add_argument(
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"--cpu",
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type=str,
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choices=list(cpu_types.keys()),
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default="atomic",
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help="CPU model to use",
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)
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parser.add_argument("--cpu-freq", type=str, default="4GHz")
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parser.add_argument(
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"--num-cores", type=int, default=1, help="Number of CPU cores"
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)
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parser.add_argument(
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"--mem-type",
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default="DDR3_1600_8x8",
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choices=ObjectList.mem_list.get_names(),
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help="type of memory to use",
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)
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parser.add_argument(
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"--mem-channels", type=int, default=2, help="number of memory channels"
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)
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parser.add_argument(
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"--mem-ranks",
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type=int,
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default=None,
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help="number of memory ranks per channel",
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)
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parser.add_argument(
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"--mem-size",
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action="store",
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type=str,
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default="2GiB",
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help="Specify the physical memory size",
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)
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parser.add_argument(
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"--tarmac-gen",
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action="store_true",
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help="Write a Tarmac trace.",
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)
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parser.add_argument(
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"--tarmac-dest",
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choices=TarmacDump.vals,
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default="stdoutput",
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help="Destination for the Tarmac trace output. [Default: stdoutput]",
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)
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parser.add_argument(
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"-P",
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"--param",
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action="append",
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default=[],
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help="Set a SimObject parameter relative to the root node. "
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"An extended Python multi range slicing syntax can be used "
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"for arrays. For example: "
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"'system.cpu[0,1,3:8:2].max_insts_all_threads = 42' "
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"sets max_insts_all_threads for cpus 0, 1, 3, 5 and 7 "
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"Direct parameters of the root object are not accessible, "
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"only parameters of its children.",
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)
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args = parser.parse_args()
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# Create a single root node for gem5's object hierarchy. There can
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# only exist one root node in the simulator at any given
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# time. Tell gem5 that we want to use syscall emulation mode
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# instead of full system mode.
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root = Root(full_system=False)
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# Populate the root node with a system. A system corresponds to a
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# single node with shared memory.
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root.system = create(args)
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root.apply_config(args.param)
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# Instantiate the C++ object hierarchy. After this point,
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# SimObjects can't be instantiated anymore.
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m5.instantiate()
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# Start the simulator. This gives control to the C++ world and
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# starts the simulator. The returned event tells the simulation
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# script why the simulator exited.
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event = m5.simulate()
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# Print the reason for the simulation exit. Some exit codes are
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# requests for service (e.g., checkpoints) from the simulation
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# script. We'll just ignore them here and exit.
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print(f"{event.getCause()} ({event.getCode()}) @ {m5.curTick()}")
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if __name__ == "__m5_main__":
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main()
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