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from .....utils.override import overrides
from .....processors.abstract_core import AbstractCore
from .....isas import ISA
from ..abstract_l1_cache import AbstractL1Cache

from m5.objects import (
    MessageBuffer,
    RubyCache,
    ClockDomain,
)


class L1Cache(AbstractL1Cache):
    def __init__(
        self,
        size: str,
        assoc: int,
        network,
        core: AbstractCore,
        cache_line_size,
        target_isa: ISA,
        clk_domain: ClockDomain,
    ):
        super(L1Cache, self).__init__(network, cache_line_size)

        self.cacheMemory = RubyCache(
            size=size, assoc=assoc, start_index_bit=self.getBlockSizeBits()
        )

        self.clk_domain = clk_domain
        self.send_evictions = self.sendEvicts(core=core, target_isa=target_isa)

    @overrides(AbstractL1Cache)
    def connectQueues(self, network):
        self.mandatoryQueue = MessageBuffer()
        self.requestFromCache = MessageBuffer(ordered=True)
        self.requestFromCache.out_port = network.in_port
        self.responseFromCache = MessageBuffer(ordered=True)
        self.responseFromCache.out_port = network.in_port
        self.forwardToCache = MessageBuffer(ordered=True)
        self.forwardToCache.in_port = network.out_port
        self.responseToCache = MessageBuffer(ordered=True)
        self.responseToCache.in_port = network.out_port