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def upgrader(cpt):
    """
    Update the checkpoint to support initial RVV implemtation.
    The updater is taking the following steps.

    1) Set vector registers to occupy 1280 bytes (40regs * 32bytes)
    2) Clear vector_element, vector_predicate and matrix registers
    3) Add RVV misc registers in the checkpoint
    """

    import re

    for sec in cpt.sections():
        # Search for all XC sections
        res = re.search(r"(.*processor.*\.core.*)\.xc.*", sec)
        if res and cpt.get(res.groups()[0] + ".isa", "isaName") == "riscv":
            # Only update for RISCV XCs
            # Updating RVV vector registers (dummy values)
            # Assuming VLEN = 256 bits (32 bytes)
            mr = cpt.get(sec, "regs.vector").split()
            if len(mr) <= 8:
                cpt.set(sec, "regs.vector", " ".join("0" for i in range(1280)))

            # Updating RVV vector element (dummy values)
            cpt.set(sec, "regs.vector_element", "")

            # Updating RVV vector predicate (dummy values)
            cpt.set(sec, "regs.vector_predicate", "")

            # Updating RVV matrix (dummy values)
            cpt.set(sec, "regs.matrix", "")

        # Search for all ISA sections
        if (
            re.search(r".*processor.*\.core.*\.isa$", sec)
            and cpt.get(sec, "isaName") == "riscv"
        ):
            # Updating RVV misc registers (dummy values)
            mr = cpt.get(sec, "miscRegFile").split()
            if len(mr) == 164:
                print(
                    "MISCREG_* RVV registers already seem " "to be inserted."
                )
            else:
                # Add dummy value for MISCREG_VSTART
                mr.insert(121, 0)
                # Add dummy value for MISCREG_VXSAT
                mr.insert(121, 0)
                # Add dummy value for MISCREG_VXRM
                mr.insert(121, 0)
                # Add dummy value for MISCREG_VCSR
                mr.insert(121, 0)
                # Add dummy value for MISCREG_VL
                mr.insert(121, 0)
                # Add dummy value for MISCREG_VTYPE
                mr.insert(121, 0)
                # Add dummy value for MISCREG_VLENB
                mr.insert(121, 0)
                cpt.set(sec, "miscRegFile", " ".join(str(x) for x in mr))


legacy_version = 17