# -*- mode:python -*- # Copyright (c) 2023-2024 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall # not be construed as granting a license to any other intellectual # property including but not limited to intellectual property relating # to a hardware implementation of the functionality of the software # licensed hereunder. You may use the software subject to the license # terms below provided that you ensure that this notice is replicated # unmodified and in its entirety in all distributions of the software, # modified or unmodified, in source code or in binary form. # # Copyright (c) 2006 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer; # redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution; # neither the name of the copyright holders nor the names of its # contributors may be used to endorse or promote products derived from # this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Import('*') SimObject('Cache.py', sim_objects=[ 'WriteAllocator', 'BaseCache', 'Cache', 'NoncoherentCache'], enums=['Clusivity']) Source('base.cc') Source('cache.cc') Source('cache_blk.cc') Source('mshr.cc') Source('mshr_queue.cc') Source('noncoherent_cache.cc') Source('write_queue.cc') Source('write_queue_entry.cc') DebugFlag('Cache') DebugFlag('CacheComp') DebugFlag('CachePort') DebugFlag('CacheRepl') DebugFlag('CacheTags') DebugFlag('CacheVerbose') DebugFlag('HWPrefetch') DebugFlag('MSHR') DebugFlag('HWPrefetchQueue') DebugFlag('PartitionPolicy') # CacheTags is so outrageously verbose, printing the cache's entire tag # array on each timing access, that you should probably have to ask for # it explicitly even above and beyond CacheAll. CompoundFlag('CacheAll', ['Cache', 'CacheComp', 'CachePort', 'CacheRepl', 'CacheVerbose', 'HWPrefetch', 'MSHR', 'PartitionPolicy'])