# Copyright (c) 2005-2007 The Regents of The University of Michigan
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from m5.SimObject import SimObject
from m5.params import *
from m5.objects.PciDevice import PciDevice, PciIoBar

class IdeID(Enum): vals = ['device0', 'device1']

class IdeDisk(SimObject):
    type = 'IdeDisk'
    cxx_header = "dev/storage/ide_disk.hh"
    cxx_class = 'gem5::IdeDisk'
    delay = Param.Latency('1us', "Fixed disk delay in microseconds")
    driveID = Param.IdeID('device0', "Drive ID")
    image = Param.DiskImage("Disk image")

class IdeController(PciDevice):
    type = 'IdeController'
    cxx_header = "dev/storage/ide_ctrl.hh"
    cxx_class = 'gem5::IdeController'
    disks = VectorParam.IdeDisk("IDE disks attached to this controller")

    VendorID = 0x8086
    DeviceID = 0x7111
    Command = 0x0
    Status = 0x280
    Revision = 0x0
    ClassCode = 0x01
    SubClassCode = 0x01
    ProgIF = 0x85
    InterruptLine = 0x1f
    InterruptPin = 0x01

    # Primary
    BAR0 = PciIoBar(size='8B')
    BAR1 = PciIoBar(size='4B')
    # Secondary
    BAR2 = PciIoBar(size='8B')
    BAR3 = PciIoBar(size='4B')
    # DMA
    BAR4 = PciIoBar(size='16B')

    io_shift = Param.UInt32(0x0, "IO port shift");
    ctrl_offset = Param.UInt32(0x0, "IDE disk control offset")