# -*- mode:python -*-

# Copyright (c) 2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder.  You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

from m5.objects.BaseTLB import BaseTLB
from m5.params import *
from m5.SimObject import SimObject


class BaseMMU(SimObject):
    type = "BaseMMU"
    abstract = True
    cxx_header = "arch/generic/mmu.hh"
    cxx_class = "gem5::BaseMMU"

    itb = Param.BaseTLB("Instruction TLB")
    dtb = Param.BaseTLB("Data TLB")

    @classmethod
    def walkerPorts(cls):
        # This classmethod is used by the BaseCPU. It should return
        # a list of strings: the table walker ports to be assigned
        # to the _cached_ports variable. The method should be removed once
        # we remove the _cached_ports methodology of composing
        # cache hierarchies
        return []

    def connectWalkerPorts(self, iport, dport):
        """
        Connect the instruction and data table walkers
        to the ports passed as arguments.
        An ISA specific MMU should override
        this method, which is doing nothing to support ISAs
        not implementing a table walker

        :param iport: Port to be connected to the instruction
                      table walker port
        :param dport: Port to be connected to the data
                      table walker port
        """
        pass