59df95c7e6
Consolidated the microcode assembler to help separate it from more x86-centric stuff.
Gabe Black
2007-04-06 16:39:25 +00:00
2a1c102f25
Refactored the x86 isa description some more. There should be more seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere.
Gabe Black
2007-04-06 16:00:56 +00:00
75e8838ba4
Clean up the code a little, fix (I think) a perceived problem with immediate sizes, and sign extend the 32-bit-acting-like-64-bit-immediates.
Gabe Black
2007-04-06 15:19:23 +00:00
e633e23a3a
Add in a stub merging function
Gabe Black
2007-04-06 15:16:36 +00:00
47c24ff07a
Clean up the macroop code.
Gabe Black
2007-04-06 15:15:36 +00:00
3c9768e644
Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
Gabe Black
2007-04-06 14:37:46 +00:00
077183f7ec
Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
Gabe Black
2007-04-05 11:35:31 +00:00
ff7b89beee
The process of going from an instruction definition to an instruction to be returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst.
Gabe Black
2007-04-04 23:35:20 +00:00
ab2bed349b
Fix a regular expression problem when recognizing labels for string substitution.
Gabe Black
2007-04-04 23:19:32 +00:00
a664017c2a
Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
Gabe Black
2007-04-04 20:50:49 +00:00
3d2a434e42
Updates for other ISA cpu_builders.
Kevin Lim
2007-04-04 16:50:48 -04:00
b247e02f6e
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
Kevin Lim
2007-04-04 15:39:13 -04:00
6ff6621f20
Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.
Kevin Lim
2007-04-04 15:38:59 -04:00
d9ab45d066
Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/work/m5.newmem
Ali Saidi
2007-04-04 13:57:23 -04:00
d0ea8ff088
The MemoryObject tha owns a port should delete it if it so chooses when deletePortRefs() is called on it with that port as a parameter. In this way a MemoryObject can keep a functional port around and give it to anyone who wants to do functional accesses rather than creating a new one each time.
Ali Saidi
2007-04-04 13:56:38 -04:00
4285990a96
Reworking how x86's isa description works. I'm adopting the following definitions to make figuring out what's what a little easier:
Gabe Black
2007-04-04 14:31:59 +00:00
7f5409f2ba
Make "Name" really be the same as "name" with only the first letter capitalized. Before, it had the first letter capitalized but all the others lower case
Gabe Black
2007-04-04 14:28:43 +00:00
65fedeb5a7
Made x86 ExtMachInsts distinguishable from each other by defining a real == and a real hash function.
Gabe Black
2007-04-04 14:27:00 +00:00
6010c6ded4
Added all the different variations of the register names.
Gabe Black
2007-04-04 14:25:36 +00:00
9e1f3bc11a
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
Kevin Lim
2007-04-04 00:14:44 -04:00
10fe8b05db
Made the "data" field of store queue entries into a character array. It's sized to match an IntReg which was what it used to be, but we might want to make it something architecture independent. All data is now endian converted before entering the store queue entries which simplifies store to load forwarding in "trans endian" simulations, and makes twin memory ops work.
Gabe Black
2007-04-03 22:53:26 +00:00
30f101881f
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem into zizzer.eecs.umich.edu:/tmp/newmem.1449b
Ali Saidi
2007-04-03 18:29:09 -04:00
4c555cffa9
fixed sttw instruction changes execution trace a bit
Ali Saidi
2007-04-03 18:28:59 -04:00
98c8cd0b36
Fix a memory leak. Hopefully this fixes the longer running benchmarks.
Kevin Lim
2007-04-03 14:25:24 -04:00
93d4c624c5
Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
Gabe Black
2007-04-03 15:01:36 +00:00
61c56ffeaf
A batch of changes and fixes. Macroops are now generated automatically, multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented.
Gabe Black
2007-04-03 15:01:09 +00:00
0ce6936e7d
Zero out ModRM if the byte isn't there, and fix some displacement size stuff.
Gabe Black
2007-04-03 14:56:24 +00:00
ec09e5ad6f
Remove/comment out DPRINTFs that were causing a segfault.
Kevin Lim
2007-04-02 13:55:45 -04:00
24cc5227af
Fix up SPARC's CPU builder to match changes to Alpha's CPU builder.
Kevin Lim
2007-04-02 13:28:17 -04:00
5c97b56eb5
Update refs for recent changes.
Kevin Lim
2007-03-30 16:59:40 -04:00
c46e946c94
Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/work/m5.newmem
Ali Saidi
2007-03-29 22:01:34 -04:00
528694817f
make serialization at least seem to work
Ali Saidi
2007-03-29 22:00:01 -04:00
ac191ecc78
Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
Gabe Black
2007-03-29 22:43:38 +00:00
1d3253abfe
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-mcf
Gabe Black
2007-03-29 17:43:37 -05:00
db6ed0eee2
Added SPARC_SE simple timing twolf regression.
Gabe Black
2007-03-29 17:41:20 -05:00
85c1e89444
Added a SPARC_SE simple timing mcf regression.
Gabe Black
2007-03-29 17:39:34 -05:00
8ca218cab5
get rid of CWP bounds warning...
Ali Saidi
2007-03-29 15:57:11 -04:00
370b712360
add to instruction test sttw instruction
Ali Saidi
2007-03-29 15:41:09 -04:00
7fcc9d2106
Made the MultiOp format do a little more. It now sets up single microop instructions to return an instance of the right class. The code to decode register numbers and generate loads and stores still needs to be added. Also, a syntax for specifying operands as sources, destinations, or both needs to be established. Multipl microop instructions are also not handled, pending real macroop generation support.
Gabe Black
2007-03-29 17:57:19 +00:00
e67a207ad3
Add a microcode assembler. A microcode "program" is a series of statements. Each statement has an optional label at the beginning, a capitilized microcode class name which is roughly equivalent to a mnemonic in a regular ISA, and then an optional series of operands seperated by white space. The operands are either a decimal constant, a label, or a code fragment surrounded by non nested {}s. Labels are a letter or underscore followed by letters, underscores, or digits. The syntax for describing code segments might need to be changed if a need arrises to have {}s in the code itself.
Gabe Black
2007-03-29 17:57:18 +00:00
5c4cc4b552
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-vortex
Gabe Black
2007-03-29 12:57:17 -05:00
0f2201c1fe
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-vortex
Gabe Black
2007-03-29 12:53:36 -05:00
484214db78
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-gzip
Gabe Black
2007-03-29 12:52:09 -05:00
d3b0ea3eeb
Added SPARC_SE simple timing vortex regression.
Gabe Black
2007-03-29 12:51:12 -05:00
7fd748d7fc
Added SPARC_SE simple timing gzip regression.
Gabe Black
2007-03-29 12:49:59 -05:00
5c3f724174
Override addPrivateSplitL1Caches function in order to automatically set the tgts_per_mshr of the caches to 20. This is needed otherwise things will potentially lock up when using the O3CPU because the caches can run out of targets, and then not respond.
Kevin Lim
2007-03-29 12:25:47 -04:00
80af6530f6
Update code so that the O3 CPU can handle not initially having anything hooked up to its ports. This fixes the segfault Ali recently found when using sampling.
Kevin Lim
2007-03-29 12:02:57 -04:00
14a7cda195
Merge zizzer.eecs.umich.edu:/bk/newmem into ewok.(none):/home/gblack/m5/newmem-x86
Gabe Black
2007-03-29 00:51:34 -07:00
77ce05f478
Fidget with the syntax of the MultiOp format in anticipation of making it actually work.
Gabe Black
2007-03-29 00:50:54 -07:00
fd77212b72
Add code to generate register and immediate based integer op microop classes.
Gabe Black
2007-03-29 00:49:53 -07:00
0d5f6167ff
Allow "let" blocks to add code to the output files.
Gabe Black
2007-03-29 00:47:46 -07:00
8a674bed5c
Call compare and Swap on the target, not the response.
Ron Dreslinski
2007-03-28 14:38:11 -05:00
e95bc9d8f9
some more fixes... non-tso stuff seems to work
Ali Saidi
2007-03-27 20:44:21 -04:00
55614caecc
Merge zizzer:/bk/newmem into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head
Ron Dreslinski
2007-03-27 17:06:07 -05:00
6b8cd9d06d
First Pass At Cmp/Swap in caches
Ron Dreslinski
2007-03-27 17:05:25 -05:00
d8ca2d3b16
Instead of creating a new python process to run traceflags.py, just directly exec the file and generate the flags
Nathan Binkert
2007-03-26 21:07:32 -07:00
01ac962a06
Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/work/m5.newmem
Ali Saidi
2007-03-26 18:40:30 -04:00
e8dc1723ee
first bit of life from the intel gigabit model
Ali Saidi
2007-03-26 18:40:18 -04:00
4e0ec56868
Update stats for changes.
Kevin Lim
2007-03-25 01:05:48 -04:00
5c044cf1f6
Update for new trace data behavior.
Kevin Lim
2007-03-24 23:47:14 -05:00
4bad33ce9d
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2
Kevin Lim
2007-03-24 14:00:16 -04:00
5e61e07613
Added a SPARC_SE simple atomic regression for the mcf benchmark.
Gabe Black
2007-03-24 02:14:24 -05:00
e7bbd85ae6
Merge zizzer.eecs.umich.edu:/bk/newmem into zower.eecs.umich.edu:/home/gblack/m5/newmem-o3-spec
Gabe Black
2007-03-23 21:47:03 -04:00
047f77102b
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2
Kevin Lim
2007-03-23 13:20:19 -04:00
2330adfa28
Make hardware loads/stores serializing; they need to avoid certain out-of-order interactions in the 21264.
Kevin Lim
2007-03-23 13:14:05 -04:00
941d3168d0
Updates for commit. 1. Move interrupt handling to a separate function to clean up main commit() function a bit. Also gate the function call off properly based on whether or not there are outstanding interrupts, and the system is not in PAL mode. 2. Better handling of updating instruction's status bits. Instructions are not marked "atCommit" until other stages view it (pushed off to IEW/IQ), and they have been properly handled (faults). 3. Don't consider the ROB "empty" for the purpose of other stages until the ROB is empty, all stores have written back, and there was no store commits this cycle. The last is necessary in case a store committed, in which case it would look like all stores have written back but in actuality have not.
Kevin Lim
2007-03-23 13:13:10 -04:00
78de00091b
3 memory system fixes: 1. Update packet's flags properly when a snoop happens 2. Don't allow accesses to read a block's data if the block has outstanding MSHRs. This avoids a RAW hazard in MP systems that the memory system was not detecting properly earlier (a write required a block to upgrade, and while the upgrade was outstanding, a read came along and read old data). 3. Update MSHR's request upon a response being handled. If the MSHR has more targets than it can respond to in one cycle, then its request must be properly updated to the new head of the targets list.
Kevin Lim
2007-03-23 13:09:37 -04:00
e21878c3f2
Handle status bits a little better, as well as non-speculative instructions.
Kevin Lim
2007-03-23 11:40:53 -04:00
31e78b0b92
Two fixes: 1. Requests are handled more properly now. They assume the memory system takes control of the request upon sending out an access. 2. load-load ordering is maintained.
Kevin Lim
2007-03-23 11:33:08 -04:00
abb07d9da3
Set progress_interval in terms of CPU cycles.
Kevin Lim
2007-03-23 11:26:30 -04:00
55a45d3644
A couple of minor fixes. 1. Set CPU ID in all modes for the O3 CPU. 2. Use nextCycle() function to prevent phase drift in O3 CPU. 3. Remove assertion in rename map that is no longer true.
Kevin Lim
2007-03-23 11:22:43 -04:00
2c47413a7a
Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/work/m5.newmem
Ali Saidi
2007-03-22 18:39:51 -04:00
12b7ebcbca
finish up the coding of the Intel Gb NIC... Many Many bugs to squash
Ali Saidi
2007-03-22 18:39:41 -04:00
e3d3ab4513
Add structure based bitfield syntax to the isa_parser. This is primarily useful for x86.
Gabe Black
2007-03-22 04:10:57 +00:00
39182808bc
Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
Gabe Black
2007-03-22 04:10:56 +00:00
10adec5b53
Merge zizzer.eecs.umich.edu:/bk/newmem into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
Gabe Black
2007-03-22 00:10:55 -04:00
39c4ea3473
Fix mcf benchmark object so it gets the arguments it expects.
Gabe Black
2007-03-22 00:10:47 -04:00
276f6d794d
Add a junk operand. With no operands, the parser breaks.
Gabe Black
2007-03-21 21:09:24 +00:00
bbffaa8ee0
Start implementing groups of instructions which do the same thing on different sets of inputs.
Gabe Black
2007-03-21 21:07:43 +00:00
1707aa750f
put the int register count in intregs.hh
Gabe Black
2007-03-21 21:04:54 +00:00
bf8b2e12ea
Add a s SPARC_SE gzip regression
Gabe Black
2007-03-21 14:31:48 -05:00
0a80d06dea
Break out the one and two byte opcodes into different files. Also change what bits decode is done on to reflect where clumps of instructions are.
Gabe Black
2007-03-21 19:19:53 +00:00
3efec59fc5
Missed a const
Gabe Black
2007-03-21 19:15:40 +00:00
390b868c87
created SPARC_SE vortex regression.
Gabe Black
2007-03-21 01:22:22 -05:00
63e2d3dcbf
Merge zizzer.eecs.umich.edu:/bk/newmem into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
Gabe Black
2007-03-21 01:18:55 -04:00
2b4c02b829
The m5 side of statetrace. This is fairly ugly, but I don't want to lose it.
Gabe Black
2007-03-21 01:18:47 -04:00
475d36ee93
Ignore "time" and "times" syscalls.
Gabe Black
2007-03-20 23:53:52 -04:00
076fd9a707
Fixed up some types and const placement, and added signed bitfields that sign extend themselves.
Gabe Black
2007-03-20 11:40:30 +00:00
e7b015cee1
Added syntax for structure oriented extMachInsts.
Gabe Black
2007-03-20 06:08:52 +00:00
4df9411e59
Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
Gabe Black
2007-03-19 17:13:23 +00:00
be3550dfe0
Ditched read or write only subbitfields for now since they were proving difficult to implement. Allow component Bitfields to be instantiated without templates, clean up the implementation a little, and adjust the comments to match.
Gabe Black
2007-03-19 17:12:50 +00:00
277ded3de7
For the _BitfieldRO and _BitfieldWO classes, make sure the undesired operator is redefined as private.
Gabe Black
2007-03-19 14:28:19 +00:00
898652fe04
Formatting fixes.
Gabe Black
2007-03-19 14:22:28 +00:00
43dea39dd4
Lots and lots of comments.
Gabe Black
2007-03-19 14:20:27 +00:00
ad9ab66175
Reworked the BitUnion stuff a bit. There is moderately better isolation of the backend parts, although there are still macros.
Gabe Black
2007-03-19 13:28:36 +00:00
7c0825ccf9
Compile fixes for SPARC_FS.
Gabe Black
2007-03-18 23:09:51 -04:00
a1f92af0fb
The syntax used for twin stores was confusing the parser so it's now broken down farther.
Gabe Black
2007-03-17 21:23:03 -04:00
594c415a0d
Created BitUnion type which lets you define nested bitfields for an integer in a portable way.
Gabe Black
2007-03-17 23:33:00 +00:00
b54fa0edda
Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
Gabe Black
2007-03-16 10:57:52 +00:00
725ee42ba7
Fix ALPHA_FS compile. The MachInst -> StaticInstPtr constructor is no longer a conversion constructor because it caused ambiguous conversions when setting the pointer to NULL.
Gabe Black
2007-03-16 10:57:34 +00:00
Gabe Black