derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Commit Graph

  • 99310a1d93 Make instructions that conditionally set registers set them to their old value if they don't actually execute. Gabe Black 2007-07-18 17:46:38 -07:00
  • 776283cff8 Fix the overload which prints ExtMachInst in X86. Gabe Black 2007-07-18 17:45:43 -07:00
  • 05a33a443f Make store microops actually store instead of load. Gabe Black 2007-07-18 17:45:06 -07:00
  • e209fce9de Fix a comment to refer to the right type of instruction. Gabe Black 2007-07-18 17:44:12 -07:00
  • 17f3da6c29 Fix the panic in the "error" format for x86, Gabe Black 2007-07-18 17:43:30 -07:00
  • 6c54b654a8 Implement some forms of add. Gabe Black 2007-07-18 16:33:56 -07:00
  • bafb7ee5c1 Fix the operand types in a section of the decoder. Gabe Black 2007-07-18 16:26:52 -07:00
  • b949458d4c Make the data size used by regops overridable in the microassembly. Gabe Black 2007-07-18 16:26:17 -07:00
  • 387f00e3dd Fill out the miscreg file and add types to miscregs.hh Gabe Black 2007-07-18 16:12:39 -07:00
  • 5cca5ca3d9 Hook x86 nop into the decoder. Gabe Black 2007-07-18 16:11:52 -07:00
  • d21c16fd37 Fix a compilation error for SubBitUnions, Gabe Black 2007-07-18 16:11:16 -07:00
  • 3bd42af99e Implement the x86 nop to be a "fault" microop which returns "NoFault". Gabe Black 2007-07-18 16:10:44 -07:00
  • dffc40ff62 Add a generateDisassembly function to the MicroFault StaticInst. Gabe Black 2007-07-18 16:09:35 -07:00
  • 6fbcb225af Make name, isMachineCheckFault, and isAlignmentFault const. Gabe Black 2007-07-18 16:09:00 -07:00
  • 85f32920fb Calculate the correct address size. Gabe Black 2007-07-17 20:54:55 -07:00
  • e524240d68 Make disassembled x86 register indices reflect their size. This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly. Gabe Black 2007-07-17 18:12:33 -07:00
  • 2e80f71dcd Implemented jnz. Gabe Black 2007-07-17 16:55:33 -07:00
  • 62ffc71fab Use limm to set up immediate value for subtract instruction. Gabe Black 2007-07-17 16:50:13 -07:00
  • d77d4c04b7 Implement the jz instruction. Gabe Black 2007-07-17 15:36:45 -07:00
  • c4004482a5 Make "test" set some condition codes. It still needs to zero the overflow and carry flags to be correct. Gabe Black 2007-07-17 15:35:34 -07:00
  • a6757095c3 Add in support for condition code flags. Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented. Gabe Black 2007-07-17 15:33:18 -07:00
  • cf846d5205 Add in operand which holds the condition code bits of the flag register. Gabe Black 2007-07-17 15:28:48 -07:00
  • bbf7163dd9 Add symbols for each of the flags a microop could set and each condition it could check. Gabe Black 2007-07-17 15:27:28 -07:00
  • cbc24d6600 Actually include miscregs.hh Gabe Black 2007-07-17 13:30:23 -07:00
  • b0643a08a3 Create a file to describe misc registers. Define bitfields, indices, etc. Gabe Black 2007-07-17 13:29:40 -07:00
  • 8f3153ffb3 Create a file of functions for computing condition codes. These haven't been very thuroughly tested, so use at your own risk. Gabe Black 2007-07-17 13:28:03 -07:00
  • aad11bf879 Add a spot for the condition code portion of the flag register. This is stored in the integer register file so that it can be renamed, but it should be a misc reg. Gabe Black 2007-07-17 13:26:06 -07:00
  • 13ccac1a3c Add a conversion constructor so a bitunion can be initialized to a value. Previously, the bitunion would need to be declared and then assigned to separately. Gabe Black 2007-07-17 13:23:42 -07:00
  • a67a0025b3 Make sure responses never get blocked. Steve Reinhardt 2007-07-17 08:15:23 -07:00
  • a25f3ac67f Forward cache-to-cache responses through other caches. Steve Reinhardt 2007-07-17 06:33:28 -07:00
  • ff13827ccb Assert that an mshr has a target in getTarget(). Steve Reinhardt 2007-07-17 06:23:11 -07:00
  • f67c8b33cc Fix bug with timing snoop upcalls to MemTest object. Steve Reinhardt 2007-07-15 21:03:12 -07:00
  • e80ab26abc Add valgrind-suppressions file. Steve Reinhardt 2007-07-15 23:30:22 -04:00
  • d5bb145590 Merge from head. Steve Reinhardt 2007-07-15 23:22:04 -04:00
  • 884807a68a Fix up a bunch of multilevel coherence issues. Atomic mode seems to work. Timing is closer but not there yet. Steve Reinhardt 2007-07-15 20:11:06 -07:00
  • f790f34fe3 Make Bus::findPort() a little more useful. Move check for loops outside, since half the call sites end up working around it anyway. Return integer port ID instead of port object pointer. Steve Reinhardt 2007-07-15 20:09:03 -07:00
  • 9172876dd7 Fix problem with unset max_loads in memtest. Also make default 0, and make that mean run forever. Steve Reinhardt 2007-07-15 14:32:55 -07:00
  • b1bdc3b3d9 Punt on old -n/-c memtest args. Also added comments to document treespec format. Steve Reinhardt 2007-07-15 14:07:31 -07:00
  • ad560a6642 Add --force-bus option to memtest.py. Steve Reinhardt 2007-07-15 13:22:49 -07:00
  • 4bcfa916f1 New tree-based algorithm for creating more complex cache hierarchies. Steve Reinhardt 2007-07-14 23:49:24 -07:00
  • 658eeee507 Handle broken swig version that prints version info on stderr. Steve Reinhardt 2007-07-14 21:35:26 -04:00
  • 873b762d4b Move bitunion code into it's own file. Gabe Black 2007-07-14 17:28:26 -07:00
  • 4f7809d5e6 Pull some hard coded base classes out of the isa description. Gabe Black 2007-07-14 17:14:19 -07:00
  • 15a51d0cae Add CacheRepl trace flag and move a couple DPRINTFs to it. Steve Reinhardt 2007-07-14 13:28:52 -07:00
  • abd194df5c Move a couple of DPRINTFs from Cache to CachePort. Steve Reinhardt 2007-07-14 13:16:58 -07:00
  • 3b4ff75939 Fix bug in copying packet with static data pointer. Steve Reinhardt 2007-07-14 13:14:53 -07:00
  • 288f9cf7d2 Merge from head. Steve Reinhardt 2007-07-14 12:23:47 -07:00
  • e5ecfa2745 Disable PrintThreadInfo since it causes a panic when using VPtr. See Flyspray #281. Steve Reinhardt 2007-07-14 12:22:04 -07:00
  • c2ee69d687 Make NO_FAST_ALLOC compile. Steve Reinhardt 2007-07-14 12:12:46 -07:00
  • a51e16dc89 Merge of DPRINTF fixes from head. Steve Reinhardt 2007-07-14 12:09:37 -07:00
  • 7cd6c7ee05 Fix & tweak DPRINTFs for tracediff w/new cache code. Note that we should *not* print pointer values in DPRINTFs as these needlessly clutter tracediff output. Steve Reinhardt 2007-07-14 11:48:30 -07:00
  • b4178269df Merge in .hgignore from head. Steve Reinhardt 2007-07-14 02:04:52 -04:00
  • 855b3216f2 Merge with head Steve Reinhardt 2007-07-13 22:57:36 -07:00
  • 92bb9242fb ignore stuff that we don't want to see in the status Nathan Binkert 2007-07-13 22:39:41 -07:00
  • 2c8b9cbd7f transfer tags Nathan Binkert 2007-07-13 22:24:04 -07:00
  • 4738649e32 Delete packets when we're done with them. Steve Reinhardt 2007-07-03 00:40:31 -04:00
  • 4b68652c87 Couple more minor bug fixes for FS timing mode. Steve Reinhardt 2007-07-02 13:57:45 -07:00
  • e9c04dad60 Fix a couple LL/SC bugs that only affected timing mode. Steve Reinhardt 2007-07-02 09:26:36 -07:00
  • ffd697e149 bus.cc: Fix atomic timing issue. Steve Reinhardt 2007-07-02 01:02:35 -07:00
  • 3ad761bc8e Make CPU models use new LoadLockedReq/StoreCondReq commands. Steve Reinhardt 2007-06-30 20:35:42 -07:00
  • 5e59739416 Don't propagate snoops across bridges. Wouldn't work anyway. Steve Reinhardt 2007-06-30 18:03:17 -07:00
  • 07f091d6ed Get rid of remaining traces of obsolete CoherenceProtocol object. Steve Reinhardt 2007-06-30 17:59:45 -07:00
  • 2447abe5ce Can only call makeAtomicResponse() once... Steve Reinhardt 2007-06-30 17:56:30 -07:00
  • d10a843723 Get rid of obsolete fixPacket() functions. Handled by Packet::checkFunctional() now. Steve Reinhardt 2007-06-30 17:51:29 -07:00
  • ee54ad318a Event descriptions should not end in "event" (they function as adjectives not nouns) Steve Reinhardt 2007-06-30 17:45:58 -07:00
  • f0c4dd7920 Factor out a little more common code. Steve Reinhardt 2007-06-30 13:56:25 -07:00
  • 6babda7123 Fix up a few statistics problems. Stats pretty much line up with old code, except: - bug in old code included L1 latency in L2 miss time, making it too high - UniCoherence did cache-to-cache transfers even from non-owner caches, so occasionally the icache would get a block from the dcache not the L2 - L2 can now receive ReadExReq from L1 since L1s have coherence Steve Reinhardt 2007-06-30 13:34:16 -07:00
  • 6ab53415ef Get rid of Packet result field. Error responses are now encoded in cmd field. Steve Reinhardt 2007-06-30 10:16:18 -07:00
  • 749126e011 Merge vm1.(none):/home/stever/bk/newmem-head into vm1.(none):/home/stever/bk/newmem-cache2 Steve Reinhardt 2007-06-29 13:03:36 -07:00
  • 738ecc495b fix store instructions, pass fast/quick Atomic/TimingSimpleCPU regressions... Korey Sewell 2007-06-29 15:13:50 -04:00
  • 7f3dfa7c09 Merge vm1.(none):/home/stever/bk/newmem-head into vm1.(none):/home/stever/bk/newmem-cache2 Steve Reinhardt 2007-06-28 08:28:58 -07:00
  • e28cbc98a0 o3cpu build for mips Korey Sewell 2007-06-28 05:30:46 -04:00
  • 9117c94f9c Get rid of coherence protocol object. Steve Reinhardt 2007-06-27 20:54:13 -07:00
  • c4903e0882 Revamp replacement-of-upgrade handling. Steve Reinhardt 2007-06-26 23:30:30 -07:00
  • 1b20df5607 Handle deferred snoops better. Steve Reinhardt 2007-06-26 22:23:10 -07:00
  • 69ff6d9163 cache_impl.hh: Change target overflow from assertion to warning. Steve Reinhardt 2007-06-26 18:01:22 -04:00
  • 7dacbcf492 Handle replacement of block with pending upgrade. Steve Reinhardt 2007-06-26 14:53:15 -07:00
  • f697e959a1 Couple minor bug fixes... Steve Reinhardt 2007-06-25 22:23:29 -07:00
  • 529f12a531 Get rid of requestCauses. Use timestamped queue to make sure we don't re-request bus prematurely. Use callback to avoid calling sendRetry() recursively within recvTiming. Steve Reinhardt 2007-06-25 06:47:05 -07:00
  • 47bce8ef78 Better handling of deferred targets. Steve Reinhardt 2007-06-24 17:32:31 -07:00
  • 245b0bd9b9 Merge vm1.(none):/home/stever/bk/newmem-head into vm1.(none):/home/stever/bk/newmem-cache2 Steve Reinhardt 2007-06-23 13:26:30 -07:00
  • 57ff2604e5 Minor fix plus new assertion to catch similar bugs. Steve Reinhardt 2007-06-23 13:24:33 -07:00
  • ac19e0c505 FINISH off merge of mips mt/dsp isa extensions by adding the ControlBitfieldOPerand to ISA Parser. Now, while things do build, we have to fix broken functionality... Korey Sewell 2007-06-22 21:09:35 -04:00
  • c6d137f565 add Control Bitfield class Korey Sewell 2007-06-22 20:09:46 -04:00
  • ed1db23b41 Merge vm1.(none):/home/stever/bk/newmem-head into vm1.(none):/home/stever/bk/newmem-cache2 Steve Reinhardt 2007-06-22 16:13:53 -07:00
  • 753adb38d5 mips import pt. 1 Korey Sewell 2007-06-22 19:03:42 -04:00
  • 16c1b5484f Merge zizzer.eecs.umich.edu:/bk/newmem into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/newmem-o3-micro Gabe Black 2007-06-22 17:44:33 -04:00
  • 8e6abaed79 Update of reference outputs. SPARC_SE o3 gzip didn't have reference outputs, mcf has a reduced input size, and most of the other changes are for a change in how branch mispredicts work which makes things more accurate. Gabe Black 2007-06-22 15:06:10 -04:00
  • 4d1bcbcd36 Merge vm1.(none):/home/stever/bk/newmem-head into vm1.(none):/home/stever/bk/newmem-cache2 Steve Reinhardt 2007-06-22 09:24:33 -07:00
  • bdd5fd20fb Fixes to hitLatency, blocking, buffer allocation. Single-cpu timing mode seems to work now. Steve Reinhardt 2007-06-22 09:24:07 -07:00
  • 70d6044527 Make symbols for regular registers. Gabe Black 2007-06-21 20:35:27 +00:00
  • ec24de8b59 Get rid of an unnecessary include file. Gabe Black 2007-06-21 20:35:26 +00:00
  • 49490b334a Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro Gabe Black 2007-06-21 20:35:25 +00:00
  • 470a6a9a74 Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 Gabe Black 2007-06-21 20:35:23 +00:00
  • 0a879b4590 update stats for fixed nextCycle() Ali Saidi 2007-06-21 16:35:22 -04:00
  • eff122797b Merge vm1.(none):/home/stever/bk/newmem-head into vm1.(none):/home/stever/bk/newmem-cache2 Steve Reinhardt 2007-06-21 12:03:22 -07:00
  • 83af0fdcf5 Getting closer... Steve Reinhardt 2007-06-21 11:59:17 -07:00
  • 5195500cdf Use FastAlloc for Packet, Request, CoherenceState, and SenderState so we don't spend so much time calling malloc() Ali Saidi 2007-06-21 13:50:35 -04:00
  • 25e385e0cf Use the new symbols to clean up the assembler. Gabe Black 2007-06-21 15:30:05 +00:00
  • 13bf022053 Needed for last change set to work :P Gabe Black 2007-06-21 15:29:02 +00:00