Commit Graph

2 Commits

Author SHA1 Message Date
Tiago Mück
21dfaa49ca configs: changed CHI --noc-config format
Changed format from yaml to plain python. The new py configuration
file, when provided, must specialize the CHI node types defined in
configs/ruby/CHI_config.py (moved from configs/ruby/CHI.py). This
is required in order to setup the node->router bindings when the
CustomMesh topology is used.

See configs/example/noc_config/2x4.py (replaces
configs/example/noc_config/2x4.yaml) for an example.

--noc-config was also renamed to --chi-config, since the CHI node types
can be fully specialized in the configuration file.

Change-Id: Ic0c5407dba3d2483d5c30634c115b5410a5228fd
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43123
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 19:02:21 +00:00
Tiago Mück
b13b485095 configs,mem-ruby: CHI-based Ruby protocol
This patch add a new Ruby cache coherence protocol based on Arm' AMBA5
CHI specification. The CHI protocol defines and implements two state
machine types:

- Cache_Controller: generic cache controller that can be configured as:
    - Top-level L1 I/D cache
    - A intermediate level (L2, L3, ...) private or shared cache
    - A CHI home node (i.e. the point of coherence of the system and
        has the global directory)
    - A DMA requester

- Memory_Controller: implements a CHI slave node and interfaces with
    gem5 memory controller. This controller has the functionality of a
    Directory_Controller on the other Ruby protocols, except it doesn't
    have a directory.

The Cache_Controller has multiple cache allocation/deallocation
parameters to control the clusivity with respect to upstream caches.
Allocation can be completely disabled to use Cache_Controller as a
DMA requester or as a home node without a shared LLC.

The standard configuration file configs/ruby/CHI.py provides a
'create_system' compatible with configs/example/fs.py and
configs/example/se.py and creates a system with private L1/L2 caches
per core and a shared LLC at the home nodes. Different cache topologies
can be defined by modifying 'create_system' or by creating custom
scripts using the structures defined in configs/ruby/CHI.py.

This patch also includes the 'CustomMesh' topology script to be used
with CHI. CustomMesh generates a 2D mesh topology with the placement
of components manually defined in a separate configuration file using
the --noc-config parameter.
The example in configs/example/noc_config/2x4.yaml creates a simple 2x4
mesh. For example, to run a SE mode simulation, with 4 cores,
4 mem ctnrls, and 4 home nodes (L3 caches):

build/ARM/gem5.opt configs/example/se.py \
--cmd 'tests/test-progs/hello/bin/arm/linux/hello' \
--ruby --num-cpus=4 --num-dirs=4 --num-l3caches=4 \
--topology=CustomMesh --noc-config=configs/example/noc_config/2x4.yaml

If one doesn't care about the component placement on the interconnect,
the 'Crossbar' and 'Pt2Pt' may be used and they do not require the
--noc-config option.

Additional authors:
    Joshua Randall <joshua.randall@arm.com>
    Pedro Benedicte <pedro.benedicteillescas@arm.com>
    Tuan Ta <tuan.ta2@arm.com>

JIRA: https://gem5.atlassian.net/browse/GEM5-908

Change-Id: I856524b0afd30842194190f5bd69e7e6ded906b0
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42563
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 15:28:44 +00:00