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Author	SHA1	Message	Date
Andreas Sandberg	56e53cafe0	base, sim, mem, arch: Remove the dummy CPU in NULL The NULL ISA target has a dummy BaseCPU class that doesn't seem to be needed anymore. Remove this class and the some unnecessary includes. Change-Id: I031c999b3c0bb8dec036ad087a3edb2c1c723501 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34236 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>	2020-09-14 08:52:40 +00:00
Gabe Black	9a58428a2b	arch: Delete authors lists from the null arch files. Change-Id: Ief42708d8961a5c33db5e8a603ee8fff8df8b198 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25446 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>	2020-02-18 03:35:12 +00:00
Andreas Hansson	19a5b68db7	arch: Resurrect the NOISA build target and rename it NULL This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. --HG-- rename : build_opts/NOISA => build_opts/NULL rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc	2013-09-04 13:22:57 -04:00

Author

SHA1

Message

Date

Andreas Sandberg

56e53cafe0

base, sim, mem, arch: Remove the dummy CPU in NULL

The NULL ISA target has a dummy BaseCPU class that doesn't seem to be
needed anymore. Remove this class and the some unnecessary includes.

Change-Id: I031c999b3c0bb8dec036ad087a3edb2c1c723501
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34236
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-09-14 08:52:40 +00:00

Gabe Black

9a58428a2b

arch: Delete authors lists from the null arch files.

Change-Id: Ief42708d8961a5c33db5e8a603ee8fff8df8b198
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25446
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-02-18 03:35:12 +00:00

Andreas Hansson

19a5b68db7

arch: Resurrect the NOISA build target and rename it NULL

This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.

The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.

--HG--
rename : build_opts/NOISA => build_opts/NULL
rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts
rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh
rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc

2013-09-04 13:22:57 -04:00

3 Commits