Add the ability to use an address mask for symbol loading
Rather then silently failing on platform accesses panic
Move BadAddr/IsaFake no Device from Tsunami
Let the system kernel be none, but warn about it
configs/common/FSConfig.py:
We don't have a kernel for sparc yet
src/arch/sparc/system.cc:
Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
src/base/loader/aout_object.cc:
src/base/loader/aout_object.hh:
src/base/loader/ecoff_object.cc:
src/base/loader/ecoff_object.hh:
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.hh:
src/base/loader/raw_object.cc:
src/base/loader/raw_object.hh:
Add the ability to use an address mask for symbol loading
src/dev/sparc/t1000.cc:
Rather then silently failing on platform accesses panic
src/dev/sparc/t1000.hh:
fix up a couple of platform comments
src/python/m5/objects/Bus.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/T1000.py:
src/python/m5/objects/Tsunami.py:
Move BadAddr/IsaFake no Device from Tsunami
src/python/m5/objects/System.py:
Let kernel be none
src/sim/system.cc:
Let the system kernel be none, but warn about it
--HG--
extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
configs/common/FSConfig.py:
Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
Create a T1000 platform
src/arch/sparc/miscregfile.cc:
Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
Truncate an ExtMachInst to a MachInst before comparing with Legion.
--HG--
extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.
SConstruct:
Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add option to try raw when nothing works
src/cpu/exetrace.cc:
cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
change the instruction to be 32 bits because it is
src/mem/physical.cc:
fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
add the ability to add Addr() together
--HG--
extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
configs/common/Simulation.py:
simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick.
src/python/m5/__init__.py:
make a new m5 param called MaxTick.
src/sim/host.hh:
fix the M5 def. of MaxTick
src/sim/main.cc:
Simplify the MaxTick/num_cycles parsing within main.cc
--HG--
extra : convert_revision : f800addfbc1323591c2e05b892276b439b671668
src/python/m5/objects/BaseCPU.py:
These parameters should have been removed in an earlier push.
--HG--
extra : convert_revision : 781b39ca370361e9568b1af0be96ff5848b1f3f4
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
No need for specialized init() function any more.
src/python/m5/objects/Tsunami.py:
Override responder when set by user. This avoids having bus.responder floating around and not doing anything when the user has specified their own default responder.
--HG--
extra : convert_revision : c547daf15b23a889c98e62bfd53c293c85d7a041
src/SConscript:
remove pcifake and tsunami fake from sconscript
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
combine badaddr and isa fake into one
src/python/m5/objects/Pci.py:
remove pcifake
src/python/m5/objects/Tsunami.py:
make badaddr derive from isafake
--HG--
extra : convert_revision : 91470db60aa1de6b85827304e27bd3414cc9d8d1
src/mem/bus.cc:
src/mem/bus.hh:
Bus now will be setup with a default responder, unless the user overrides it. This default responder should return BadAddress if no matching port is found.
src/python/m5/objects/Bus.py:
Bus now has a default responder for FS mode if the user doesn't override it. It returns BadAddress if no matching port is found.
src/python/m5/objects/Tsunami.py:
Add bad address device. Also record when the user has specified their own default responder.
--HG--
extra : convert_revision : 59070477ae313ee711b2d59baa2369c9a91c5b85
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Use fix Packet function
src/mem/packet.cc:
Fix an assert that was checking the wrong thing
src/mem/tport.cc:
Properly detect if we need to do the access to the functional device
--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
src/python/m5/SimObject.py:
how did i not commit this already? the other way doesn't seem to work.
--HG--
extra : convert_revision : 55737d3d10742a1913a376d1febbc5809f2fab8f
configs/example/fs.py:
Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
Don't need to set console & intrcontrol cpu
params anymore (default is fixed now).
--HG--
extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
src/cpu/simple/timing.cc:
hand merge
--HG--
extra : convert_revision : 083bf102249ad9bc63c447dbf85d3863f935f647
src/python/m5/SimObject.py:
now that setMemoryMode is a method in System, need to convert the SimObject * _ccObject into a system ptr to call setMemoryMode.
src/sim/main.cc:
need this conversion now.
src/sim/sim_object.hh:
put the enum back into SimObject.
src/sim/system.hh:
memoryMode is now a part of SimObject, need the ::'s
--HG--
extra : convert_revision : 0ade06957fa57b497798e1f50c237ca1badc821d
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
Debug output.
Clean up memleak in atomic mode.
Set hitLatency.
Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
Add command strings for new commands
src/python/m5/objects/MemTest.py:
Add param to test atomic memory.
--HG--
extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
Hand merge.
--HG--
extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
src/mem/physical.cc:
Update comment to match memtest use
src/python/m5/objects/PhysicalMemory.py:
Make memtester have a way to connect functionally
tests/configs/memtest.py:
Properly create 8 memtesters and connect them to the memory system
--HG--
extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
src/cpu/SConscript:
Add memtester to the compilation environment.
Someone who knows this better should make the MemTest a cpu model parameter.
For now attached with the build of o3 cpu.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Update Memtest for new mem system
src/python/m5/objects/MemTest.py:
Update memtest python description
--HG--
extra : convert_revision : d6a63e08fda0975a7abfb23814a86a0caf53e482
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
src/mem/bus.cc:
Hand merged. Needs to be fixed
--HG--
extra : convert_revision : df03219ccfd18431cc726a063bd29d30554944a1
src/mem/bus.cc:
src/mem/bus.hh:
minor fix and some formatting changes
src/python/m5/objects/Bus.py:
changed bits to bytes
--HG--
extra : convert_revision : dcd22205604b7a2727eaf2094084c4858f3589c5
and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.
src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
Add in default FUPool.
src/python/m5/objects/O3CPU.py:
Use defaults better. Also set checker parameters, and fix up a config bug.
--HG--
extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
