3 Commits

Author SHA1 Message Date
Melissa Jost
1ff3ea2a09 tests: Fix failing SST and SystemC nightly tests
There was a bug with the SST and SystemC tests where they wouldn't
compile due to a missing path for the gdbremote/signals.hh
header, and this change includes that so they run properly.

Change-Id: I9ff0404e327358fe2d1b77388bbcc1f807136ebe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67817
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-03-30 21:01:42 +00:00
Hoa Nguyen
7bc9b0175f misc,ext: Add gem5/SST integration
Enable a gem5 system to be an SST::Component.

This change includes,
  - SST::gem5Component: responsible for,
      - initializing the Python environment for gem5
      - instantiating gem5 SimObjects
      - connecting SST::SSTResponderSubComponent to
gem5::OutgoingRequestBridge
      - hanlding the gem5 event queue (no thread-synchronization)
      - handling executing gem5 events
  - SST::SSTResponderSubComponent: responsible for,
      - receiving gem5 requests and sending the requests to
memory.
      - sending responses to the corresponding
gem5::OutgoingRequestBridge.
  - SST::SSTResponder: owned by SSTResponderSubComponent, the
actual actor that sends gem5's requests to memory.
  - gem5::OutgoingRequestBridge: receives the requests from
gem5 and sends them to SST. This SimObject allows the initialization
requests to be cached and the receiver could query the
initialization data later on.
  - gem5::SSTResponderInterface: the interface specifying how SST
communicates with gem5.
  - A working example of a gem5/SST setup.

More information is available at ext/sst/README.md.
For installation instructions, please refer to ext/sst/INSTALL.md.

Change-Id: I6b81260ef825415bcfe72b8a078854f4c94de782
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50468
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-27 04:24:15 +00:00
Curtis Dunham
f05cb84ed1 ext: Add SST connector
This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
2015-04-08 15:56:06 -05:00