diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 938904bc11..fed6dda28a 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -61,8 +61,8 @@
 0x1: decode OPCODE_OP_TOP5 {
     format WarnUnimpl {
         0x00: decode OPCODE_OP_BOTTOM3 {
-            0x4: Inst::addI(rAl,Ib);
-            0x5: Inst::addI(rAx,Iz);
+            0x4: Inst::add(rAl,Ib);
+            0x5: Inst::add(rAx,Iz);
             0x6: push_ES();
             0x7: pop_ES();
             default: MultiInst::add(OPCODE_OP_BOTTOM3,
@@ -123,8 +123,8 @@
             0x7: das();
         }
         0x06: decode OPCODE_OP_BOTTOM3 {
-            0x4: Inst::xorI(rAl,Ib);
-            0x5: Inst::xorI(rAx,Iz);
+            0x4: Inst::xor(rAl,Ib);
+            0x5: Inst::xor(rAx,Iz);
             0x6: M5InternalError::error(
                 {{"Tried to execute the SS segment override prefix!"}});
             0x7: aaa();
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 6d428881ea..b94b55aab5 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -135,36 +135,35 @@ let {{
             opNum = len(opTypes) - 1
             # A regular expression to find the operand placeholders we're
             # interested in.
-            opRe = re.compile("%%(?P<operandNum>%d)(?=[^0-9]|$)" % opNum)
+            opRe = re.compile("\\^(?P<operandNum>%d)(?=[^0-9]|$)" % opNum)
 
             # Parse the operand type strign we're working with
-            print "About to parse tag %s" % opTypes[opNum]
             opType = OpType(opTypes[opNum])
 
             if opType.reg:
                 #Figure out what to do with fixed register operands
                 if opType.reg in ("Ax", "Bx", "Cx", "Dx"):
-                    code = opRe.sub("{INTREG_R%s}" % opType.reg.upper(), code)
+                    code = opRe.sub("%%{INTREG_R%s}" % opType.reg.upper(), code)
                 elif opType.reg == "Al":
                     # We need a way to specify register width
-                    code = opRe.sub("{INTREG_RAX}", code)
+                    code = opRe.sub("%{INTREG_RAX}", code)
                 else:
                     print "Didn't know how to encode fixed register %s!" % opType.reg
             elif opType.tag == None or opType.size == None:
                 raise Exception, "Problem parsing operand tag: %s" % opType.tag
             elif opType.tag in ("C", "D", "G", "P", "S", "T", "V"):
                 # Use the "reg" field of the ModRM byte to select the register
-                code = opRe.sub("{(uint8_t)MODRM_REG}", code)
+                code = opRe.sub("%{(uint8_t)MODRM_REG}", code)
             elif opType.tag in ("E", "Q", "W"):
                 # This might refer to memory or to a register. We need to
                 # divide it up farther.
-                regCode = opRe.sub("{(uint8_t)MODRM_RM}", code)
+                regCode = opRe.sub("%{(uint8_t)MODRM_RM}", code)
                 regTypes = copy.copy(opTypes)
                 regTypes.pop(-1)
                 # This needs to refer to memory, but we'll fill in the details
                 # later. It needs to take into account unaligned memory
                 # addresses.
-                memCode = opRe.sub("0", code)
+                memCode = opRe.sub("%0", code)
                 memTypes = copy.copy(opTypes)
                 memTypes.pop(-1)
                 return doSplitDecode(name, Name, specializeInst, "MODRM_MOD",
@@ -172,16 +171,16 @@ let {{
             elif opType.tag in ("I", "J"):
                 # Immediates are already in the instruction, so don't leave in
                 # those parameters
-                code = opRe.sub("", code)
+                code = opRe.sub("${IMMEDIATE}", code)
             elif opType.tag == "M":
                 # This needs to refer to memory, but we'll fill in the details
                 # later. It needs to take into account unaligned memory
                 # addresses.
-                code = opRe.sub("0", code)
+                code = opRe.sub("%0", code)
             elif opType.tag in ("PR", "R", "VR"):
                 # There should probably be a check here to verify that mod
                 # is equal to 11b
-                code = opRe.sub("{(uint8_t)MODRM_RM}", code)
+                code = opRe.sub("%{(uint8_t)MODRM_RM}", code)
             else:
                 raise Exception, "Unrecognized tag %s." % opType.tag
             opTypes.pop(-1)
@@ -223,16 +222,24 @@ let {{
 
         def getAllocator(self, *microFlags):
             args = ''
+            signature = "<"
+            emptySig = True
             for arg in self.args:
-                if arg.has_key("operandConst"):
-                    args += ", %s" % arg["operandConst"]
-                elif arg.has_key("operandCode"):
-                    args += ", %s" % arg["operandCode"]
+                if not emptySig:
+                    signature += ", "
+                emptySig = False
+                if arg.has_key("operandImm"):
+                    args += ", %s" % arg["operandImm"]
+                    signature += ImmOpType
+                elif arg.has_key("operandReg"):
+                    args += ", %s" % arg["operandReg"]
+                    signature += RegOpType
                 elif arg.has_key("operandLabel"):
                     raise Exception, "Found a label while creating allocator string."
                 else:
                     raise Exception, "Unrecognized operand type."
-            return 'new %s(machInst%s%s)' % (self.className, self.microFlagsText(microFlags), args)
+            signature += ">"
+            return 'new %s%s(machInst%s%s)' % (self.className, signature, self.microFlagsText(microFlags), args)
 }};
 
 let {{
@@ -260,7 +267,7 @@ let{{
         # time. Each expression expects the thing it's looking for to be at
         # the beginning of the line, so the previous component is stripped
         # before continuing.
-        labelRe = re.compile(r'^[ \t]*(?P<label>[a-zA-Z_]\w*)[ \t]:')
+        labelRe = re.compile(r'^[ \t]*(?P<label>\w\w*)[ \t]:')
         lineRe = re.compile(r'^(?P<line>[^\n][^\n]*)$')
         classRe = re.compile(r'^[ \t]*(?P<className>[a-zA-Z_]\w*)')
         # This recognizes three different flavors of operands:
@@ -271,7 +278,12 @@ let{{
         #    underscore, which is optionally followed by a sequence of
         #    capital or small letters, underscores, or digts between 0 and 9
         opRe = re.compile( \
-            r'^[ \t]*((?P<operandLabel>[a-zA-Z_]\w*)|(?P<operandConst>[0-9][0-9]*)|(\{(?P<operandCode>[^}]*)\}))')
+            r'^[ \t]*((\@(?P<operandLabel0>\w\w*))|' +
+                    r'(\@\{(?P<operandLabel1>[^}]*)\})|' +
+                    r'(\%(?P<operandReg0>\w\w*))|' +
+                    r'(\%\{(?P<operandReg1>[^}]*)\})|' +
+                    r'(\$(?P<operandImm0>\w\w*))|' +
+                    r'(\$\{(?P<operandImm1>[^}]*)\}))')
         lineMatch = lineRe.search(code)
         while lineMatch != None:
             statement = MicroOpStatement()
@@ -310,9 +322,10 @@ let{{
                 # representations of operand values. Different forms might be
                 # needed in different places, for instance to replace a label
                 # with an offset.
-                for opType in ("operandLabel", "operandConst", "operandCode"):
+                for opType in ("operandLabel0", "operandReg0", "operandImm0",
+                               "operandLabel1", "operandReg1", "operandImm1"):
                     if opMatch.group(opType):
-                        statement.args[-1][opType] = opMatch.group(opType)
+                        statement.args[-1][opType[:-1]] = opMatch.group(opType)
                 if len(statement.args[-1]) == 0:
                     print "Problem parsing operand in statement: %s" \
                             % orig_line
@@ -338,7 +351,7 @@ let{{
                     # This is assuming that intra microcode branches go to
                     # the next micropc + displacement, or
                     # micropc + 1 + displacement.
-                    arg["operandConst"] = labels[arg["operandLabel"]] - micropc - 1
+                    arg["operandImm"] = labels[arg["operandLabel"]] - micropc - 1
             micropc += 1
         return statements
 }};
diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa
new file mode 100644
index 0000000000..b1351d999f
--- /dev/null
+++ b/src/arch/x86/isa/microops/base.isa
@@ -0,0 +1,172 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use.  Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+//     Director of Intellectual Property Licensing
+//     Office of Strategy and Technology
+//     Hewlett-Packard Company
+//     1501 Page Mill Road
+//     Palo Alto, California  94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.  Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution.  Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.  No right of
+// sublicense is granted herewith.  Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses.  Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+//The operand types a microop template can be specialized with
+output header {{
+    enum OperandType {
+        RegisterOperand,
+        ImmediateOperand
+    };
+}};
+
+//A class which is the base of all x86 micro ops it provides a function to
+//set necessary flags appropriately.
+output header {{
+    class X86MicroOpBase : public X86StaticInst
+    {
+      protected:
+        X86MicroOpBase(bool isMicro, bool isDelayed,
+                bool isFirst, bool isLast,
+                const char *mnem, ExtMachInst _machInst,
+                OpClass __opClass) :
+            X86StaticInst(mnem, _machInst, __opClass)
+        {
+            flags[IsMicroOp] = isMicro;
+            flags[IsDelayedCommit] = isDelayed;
+            flags[IsFirstMicroOp] = isFirst;
+            flags[IsLastMicroOp] = isLast;
+        }
+    };
+}};
+
+// This sets up a class which is templated on the type of
+// arguments a particular flavor of a microcode instruction
+// can accept. It's parameters are specialized to create polymorphic
+// behavior in microops.
+def template BaseMicroOpTemplateDeclare {{
+    template%(signature)s
+    class %(class_name)s;
+}};
+
+let {{
+    def buildBaseMicroOpTemplate(Name, numParams):
+        signature = "<"
+        signature += "int SignatureOperandTypeSpecifier0"
+        for count in xrange(1,numParams):
+            signature += \
+                ", int SingatureOperandTypeSpecifier%d" % count
+        signature += ">"
+        subs = {"signature" : signature, "class_name" : Name}
+        return BaseMicroOpTemplateDeclare.subst(subs)
+
+    RegOpType = "RegisterOperand"
+    ImmOpType = "ImmediateOperand"
+
+    def buildMicroOpTemplateDict(*params):
+        signature = "<"
+        if len(params):
+            signature += params[0]
+            if len(params) > 1:
+                for param in params[1:]:
+                    signature += ", %s" % param
+        signature += ">"
+        subs = {"param_dec" : "", "param_arg_dec" : "",
+                "param_init" : "", "signature" : signature}
+        for count in xrange(len(params)):
+            subs["param_dec"] += "uint64_t param%d;\n" % count
+            subs["param_arg_dec"] += ", uint64_t _param%d" % count
+            subs["param_init"] += ", param%d(_param%d)" % (count, count)
+        return subs
+}};
+
+// A tmeplate for building a specialized version of the microcode
+// instruction which knows specifies which arguments it wants
+def template MicroOpDeclare {{
+    template<>
+    class %(class_name)s%(signature)s : public X86MicroOpBase
+    {
+      protected:
+        %(param_dec)s
+        void buildMe();
+
+      public:
+        %(class_name)s(bool isMicro, bool isDelayed,
+                bool isFirst, bool isLast,
+                ExtMachInst _machInst %(param_arg_dec)s);
+
+        %(class_name)s(ExtMachInst _machInst %(param_arg_dec)s);
+
+        %(BasicExecDeclare)s
+    };
+}};
+
+def template MicroOpConstructor {{
+
+    inline void %(class_name)s%(signature)s::buildMe()
+    {
+        %(constructor)s;
+    }
+
+    inline %(class_name)s%(signature)s::%(class_name)s(
+            ExtMachInst machInst %(param_arg_dec)s) :
+        %(base_class)s(false, false, false, false,
+                "%(mnemonic)s", machInst, %(op_class)s)
+                %(param_init)s
+    {
+        buildMe();
+    }
+
+    inline %(class_name)s%(signature)s::%(class_name)s(
+            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
+            ExtMachInst machInst %(param_arg_dec)s)
+        : %(base_class)s(isMicro, isDelayed, isFirst, isLast,
+                "%(mnemonic)s", machInst, %(op_class)s)
+                %(param_init)s
+    {
+        buildMe();
+    }
+}};
diff --git a/src/arch/x86/isa/microops/microops.isa b/src/arch/x86/isa/microops/microops.isa
index bbf26f605a..bb136fc813 100644
--- a/src/arch/x86/isa/microops/microops.isa
+++ b/src/arch/x86/isa/microops/microops.isa
@@ -53,5 +53,8 @@
 //
 // Authors: Gabe Black
 
-//Micro ops
+//Common microop stuff
+##include "base.isa"
+
+//Integer microop definitions
 ##include "int.isa"
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 36b0ee4dfd..af469ab3de 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -96,7 +96,7 @@ def operand_types {{
 }};
 
 def operands {{
-        'IntRegOp0':     ('IntReg', 'udw', 'regIndex0', 'IsInteger', 1),
-        'IntRegOp1':     ('IntReg', 'udw', 'regIndex1', 'IsInteger', 2),
-        'IntRegOp2':     ('IntReg', 'udw', 'regIndex2', 'IsInteger', 2),
+        'IntRegOp0':     ('IntReg', 'udw', 'param0', 'IsInteger', 1),
+        'IntRegOp1':     ('IntReg', 'udw', 'param1', 'IsInteger', 2),
+        'IntRegOp2':     ('IntReg', 'udw', 'param2', 'IsInteger', 2),
 }};