diff --git a/tests/gem5/asmtest/configs/simple_binary_run.py b/tests/gem5/asmtest/configs/riscv_asmtest.py
similarity index 58%
rename from tests/gem5/asmtest/configs/simple_binary_run.py
rename to tests/gem5/asmtest/configs/riscv_asmtest.py
index 5540e806ba..e98ec1bd49 100644
--- a/tests/gem5/asmtest/configs/simple_binary_run.py
+++ b/tests/gem5/asmtest/configs/riscv_asmtest.py
@@ -31,7 +31,7 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in
 gem5 while still being functinal.
 """
 
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.components.processors.cpu_types import (
     get_cpu_types_str_set,
     get_cpu_type_from_str,
@@ -40,29 +40,13 @@ from gem5.components.memory import SingleChannelDDR3_1600
 from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.no_cache import NoCache
 from gem5.components.processors.simple_processor import SimpleProcessor
-from gem5.components.processors.base_cpu_core import BaseCPUCore
-from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
-from gem5.components.processors.simple_core import SimpleCore
-from gem5.components.boards.mem_mode import MemMode
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.simulate.simulator import Simulator
-from gem5.isas import get_isa_from_str, get_isas_str_set, ISA
-
-from m5.util import fatal
+from gem5.isas import ISA
 
 import argparse
-import importlib
-
-cpu_types_string_map = {
-    CPUTypes.ATOMIC: "AtomicSimpleCPU",
-    CPUTypes.O3: "O3CPU",
-    CPUTypes.TIMING: "TimingSimpleCPU",
-    CPUTypes.KVM: "KvmCPU",
-    CPUTypes.MINOR: "MinorCPU",
-}
 
 parser = argparse.ArgumentParser(
-    description="A gem5 script for running simple binaries in SE mode."
+    description="A gem5 script for testing RISC-V instructions"
 )
 
 parser.add_argument(
@@ -73,17 +57,6 @@ parser.add_argument(
     "cpu", type=str, choices=get_cpu_types_str_set(), help="The CPU type used."
 )
 
-parser.add_argument(
-    "isa", type=str, choices=get_isas_str_set(), help="The ISA used"
-)
-
-parser.add_argument(
-    "-b",
-    "--base-cpu-processor",
-    action="store_true",
-    help="Use the BaseCPUProcessor instead of the SimpleProcessor.",
-)
-
 parser.add_argument(
     "--riscv-32bits",
     action="store_true",
@@ -98,15 +71,6 @@ parser.add_argument(
     help="The directory in which resources will be downloaded or exist.",
 )
 
-parser.add_argument(
-    "--arguments",
-    type=str,
-    action="append",
-    default=[],
-    required=False,
-    help="The input arguments for the binary.",
-)
-
 parser.add_argument(
     "-n",
     "--num-cores",
@@ -122,45 +86,16 @@ args = parser.parse_args()
 cache_hierarchy = NoCache()
 memory = SingleChannelDDR3_1600()
 
-isa_enum = get_isa_from_str(args.isa)
-cpu_enum = get_cpu_type_from_str(args.cpu)
+processor = SimpleProcessor(
+    cpu_type=get_cpu_type_from_str(args.cpu),
+    isa=ISA.RISCV,
+    num_cores=args.num_cores,
+)
 
-if isa_enum == ISA.RISCV and args.riscv_32bits and not args.base_cpu_processor:
-    fatal("To use Riscv 32 CPU, the base_cpu_processor must be specify!")
-
-if args.base_cpu_processor:
-
-    if isa_enum == ISA.RISCV and args.riscv_32bits:
-        m5_objects = importlib.import_module("m5.objects")
-        cpu_class = getattr(
-            m5_objects, f"Riscv32{cpu_types_string_map[cpu_enum]}"
-        )
-        cores = [
-            BaseCPUCore(core=cpu_class(cpu_id=i), isa=isa_enum)
-            for i in range(args.num_cores)
-        ]
-    else:
-        cores = [
-            BaseCPUCore(
-                core=SimpleCore.cpu_simobject_factory(
-                    cpu_type=cpu_enum,
-                    isa=isa_enum,
-                    core_id=i,
-                ),
-                isa=isa_enum,
-            )
-            for i in range(args.num_cores)
-        ]
-
-    processor = BaseCPUProcessor(
-        cores=cores,
-    )
-else:
-    processor = SimpleProcessor(
-        cpu_type=cpu_enum,
-        isa=isa_enum,
-        num_cores=args.num_cores,
-    )
+if args.riscv_32bits:
+    for simple_core in processor.cores:
+        for i in range(len(simple_core.core.isa)):
+            simple_core.core.isa[i].riscv_type = "RV32"
 
 motherboard = SimpleBoard(
     clk_freq="3GHz",
@@ -170,8 +105,10 @@ motherboard = SimpleBoard(
 )
 
 # Set the workload
-binary = Resource(args.resource, resource_directory=args.resource_directory)
-motherboard.set_se_binary_workload(binary, arguments=args.arguments)
+binary = obtain_resource(
+    args.resource, resource_directory=args.resource_directory
+)
+motherboard.set_se_binary_workload(binary)
 
 # Run the simulation
 simulator = Simulator(board=motherboard)
diff --git a/tests/gem5/asmtest/tests.py b/tests/gem5/asmtest/tests.py
index 02283ec213..5822fd519c 100644
--- a/tests/gem5/asmtest/tests.py
+++ b/tests/gem5/asmtest/tests.py
@@ -182,12 +182,11 @@ for cpu_type in cpu_types:
                 "gem5",
                 "asmtest",
                 "configs",
-                "simple_binary_run.py",
+                "riscv_asmtest.py",
             ),
             config_args=[
                 binary,
                 cpu_type,
-                "riscv",
                 "--num-cores",
                 "4",
                 "--resource-directory",