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arch, arch-arm, cpu: Add matrix reg support to the ISA Parser

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The ISA parser now emits the code required to access matrix
registers. In the case where a register is both a source and a
destination, the ISA parser generates appropriate code to make sure
that the contents of the source is copied to the destination. This is
required for the O3 CPU which treats these as two different physical
registers, and hence data is lost if not explicitly preserved.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1289

Change-Id: I8796bd1ea55b5edf5fb8ab92ef1a6060ccc58fa1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64338
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Sascha Bischoff
2022-08-03 15:38:46 +01:00
committed by Giacomo Travaglini
parent 142d562b2f
commit fe8eda9c4e
6 changed files with 87 additions and 4 deletions
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5
src/cpu/FuncUnit.py
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@@ -1,4 +1,4 @@
# Copyright (c) 2010, 2017-2018 ARM Limited
# Copyright (c) 2010, 2017-2018, 2022 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -89,6 +89,9 @@ class OpClass(Enum):
"SimdShaSigma2",
"SimdShaSigma3",
"SimdPredAlu",
"Matrix",
"MatrixMov",
"MatrixOP",
"MemRead",
"MemWrite",
"FloatMemRead",

3
src/cpu/minor/BaseMinorCPU.py
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@@ -215,6 +215,9 @@ class MinorDefaultFloatSimdFU(MinorFU):
"SimdSha256Hash2",
"SimdShaSigma2",
"SimdShaSigma3",
"Matrix",
"MatrixMov",
"MatrixOP",
]
)

5
src/cpu/op_class.hh
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010, 2017-2018 ARM Limited
* Copyright (c) 2010, 2017-2018, 2022 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -99,6 +99,9 @@ static const OpClass SimdSha256Hash2Op = enums::SimdSha256Hash2;
static const OpClass SimdShaSigma2Op = enums::SimdShaSigma2;
static const OpClass SimdShaSigma3Op = enums::SimdShaSigma3;
static const OpClass SimdPredAluOp = enums::SimdPredAlu;
static const OpClass MatrixOp = enums::Matrix;
static const OpClass MatrixMovOp = enums::MatrixMov;
static const OpClass MatrixOPOp = enums::MatrixOP;
static const OpClass MemReadOp = enums::MemRead;
static const OpClass MemWriteOp = enums::MemWrite;
static const OpClass FloatMemReadOp = enums::FloatMemRead;