From 35a6fe6f3db47241dd6825225da687ee0f4c8902 Mon Sep 17 00:00:00 2001 From: Roger Chang Date: Mon, 14 Aug 2023 13:58:04 +0800 Subject: [PATCH 1/2] arhc-riscv: Check vill in vector mem instructions Any vector instructions using vtype should check vill flag is set Change-Id: Ia9a2695f3005a176422da78e6f413cc789116faa --- src/arch/riscv/isa/templates/vector_mem.isa | 29 ++++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/src/arch/riscv/isa/templates/vector_mem.isa b/src/arch/riscv/isa/templates/vector_mem.isa index 4eebb477f3..c2b382043c 100644 --- a/src/arch/riscv/isa/templates/vector_mem.isa +++ b/src/arch/riscv/isa/templates/vector_mem.isa @@ -137,6 +137,8 @@ Fault return std::make_shared( "RVV is disabled or VPU is off", machInst); } + if (machInst.vill) + return std::make_shared("VILL is set", machInst); if(!machInst.vm) { xc->getRegOperand(this, _numSrcRegs - 1, &tmp_v0); v0 = tmp_v0.as(); @@ -175,6 +177,9 @@ Fault %(op_rd)s; %(ea_code)s; + if (machInst.vill) + return std::make_shared("VILL is set", machInst); + uint32_t mem_size = width_EEW(this->machInst.width) / 8 * this->microVl; const std::vector byte_enable(mem_size, true); Fault fault = initiateMemRead(xc, EA, mem_size, memAccessFlags, @@ -297,6 +302,8 @@ Fault return std::make_shared( "RVV is disabled or VPU is off", machInst); } + if (machInst.vill) + return std::make_shared("VILL is set", machInst); if(!machInst.vm) { xc->getRegOperand(this, _numSrcRegs - 1, &tmp_v0); v0 = tmp_v0.as(); @@ -338,6 +345,8 @@ Fault RiscvISA::vreg_t tmp_v0; uint8_t *v0; + if (machInst.vill) + return std::make_shared("VILL is set", machInst); if(!machInst.vm) { xc->getRegOperand(this, _numSrcRegs - 1, &tmp_v0); v0 = tmp_v0.as(); @@ -761,6 +770,8 @@ Fault return std::make_shared( "RVV is disabled or VPU is off", machInst); } + if (machInst.vill) + return std::make_shared("VILL is set", machInst); %(op_decl)s; %(op_rd)s; constexpr uint8_t elem_size = sizeof(Vd[0]); @@ -799,7 +810,8 @@ Fault { Fault fault = NoFault; Addr EA; - + if (machInst.vill) + return std::make_shared("VILL is set", machInst); %(op_src_decl)s; %(op_rd)s; constexpr uint8_t elem_size = sizeof(Vd[0]); @@ -953,6 +965,8 @@ Fault return std::make_shared( "RVV is disabled or VPU is off", machInst); } + if (machInst.vill) + return std::make_shared("VILL is set", machInst); %(op_decl)s; %(op_rd)s; constexpr uint8_t elem_size = sizeof(Vs3[0]); @@ -987,7 +1001,8 @@ Fault { Fault fault = NoFault; Addr EA; - + if (machInst.vill) + return std::make_shared("VILL is set", machInst); RiscvISA::vreg_t tmp_v0; uint8_t *v0; if(!machInst.vm) { @@ -1126,6 +1141,8 @@ Fault return std::make_shared( "RVV is disabled or VPU is off", machInst); } + if (machInst.vill) + return std::make_shared("VILL is set", machInst); %(op_decl)s; %(op_rd)s; %(ea_code)s; @@ -1165,7 +1182,8 @@ Fault using vu = std::make_unsigned_t; Fault fault = NoFault; Addr EA; - + if (machInst.vill) + return std::make_shared("VILL is set", machInst); %(op_src_decl)s; %(op_rd)s; constexpr uint8_t elem_size = sizeof(Vd[0]); @@ -1327,6 +1345,8 @@ Fault return std::make_shared( "RVV is disabled or VPU is off", machInst); } + if (machInst.vill) + return std::make_shared("VILL is set", machInst); %(op_decl)s; %(op_rd)s; %(ea_code)s; @@ -1362,7 +1382,8 @@ Fault using vu = std::make_unsigned_t; Fault fault = NoFault; Addr EA; - + if (machInst.vill) + return std::make_shared("VILL is set", machInst); %(op_src_decl)s; %(op_rd)s; %(ea_code)s; From fe142f485ae0996009b47893f26c68985adb25c8 Mon Sep 17 00:00:00 2001 From: Roger Chang Date: Tue, 15 Aug 2023 14:13:44 +0800 Subject: [PATCH 2/2] arch-riscv: Add missing vector required check for vmem instructions The mem instructions usually executed from initiateAcc. We also need to check vector required in those instructions Change-Id: I97b4fec7fada432abb55ca58050615e12e00d1ca --- src/arch/riscv/isa/templates/vector_mem.isa | 48 +++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/src/arch/riscv/isa/templates/vector_mem.isa b/src/arch/riscv/isa/templates/vector_mem.isa index c2b382043c..1fe989ffce 100644 --- a/src/arch/riscv/isa/templates/vector_mem.isa +++ b/src/arch/riscv/isa/templates/vector_mem.isa @@ -177,6 +177,12 @@ Fault %(op_rd)s; %(ea_code)s; + MISA misa = xc->readMiscReg(MISCREG_ISA); + STATUS status = xc->readMiscReg(MISCREG_STATUS); + if (!misa.rvv || status.vs == VPUStatus::OFF) { + return std::make_shared( + "RVV is disabled or VPU is off", machInst); + } if (machInst.vill) return std::make_shared("VILL is set", machInst); @@ -345,6 +351,12 @@ Fault RiscvISA::vreg_t tmp_v0; uint8_t *v0; + MISA misa = xc->readMiscReg(MISCREG_ISA); + STATUS status = xc->readMiscReg(MISCREG_STATUS); + if (!misa.rvv || status.vs == VPUStatus::OFF) { + return std::make_shared( + "RVV is disabled or VPU is off", machInst); + } if (machInst.vill) return std::make_shared("VILL is set", machInst); if(!machInst.vm) { @@ -531,6 +543,12 @@ Fault trace::InstRecord* traceData) const { Addr EA; + MISA misa = xc->readMiscReg(MISCREG_ISA); + STATUS status = xc->readMiscReg(MISCREG_STATUS); + if (!misa.rvv || status.vs == VPUStatus::OFF) { + return std::make_shared( + "RVV is disabled or VPU is off", machInst); + } %(op_decl)s; %(op_rd)s; %(ea_code)s; @@ -651,6 +669,12 @@ Fault trace::InstRecord* traceData) const { Addr EA; + MISA misa = xc->readMiscReg(MISCREG_ISA); + STATUS status = xc->readMiscReg(MISCREG_STATUS); + if (!misa.rvv || status.vs == VPUStatus::OFF) { + return std::make_shared( + "RVV is disabled or VPU is off", machInst); + } %(op_src_decl)s; %(op_rd)s; %(ea_code)s; @@ -810,6 +834,12 @@ Fault { Fault fault = NoFault; Addr EA; + MISA misa = xc->readMiscReg(MISCREG_ISA); + STATUS status = xc->readMiscReg(MISCREG_STATUS); + if (!misa.rvv || status.vs == VPUStatus::OFF) { + return std::make_shared( + "RVV is disabled or VPU is off", machInst); + } if (machInst.vill) return std::make_shared("VILL is set", machInst); %(op_src_decl)s; @@ -1001,6 +1031,12 @@ Fault { Fault fault = NoFault; Addr EA; + MISA misa = xc->readMiscReg(MISCREG_ISA); + STATUS status = xc->readMiscReg(MISCREG_STATUS); + if (!misa.rvv || status.vs == VPUStatus::OFF) { + return std::make_shared( + "RVV is disabled or VPU is off", machInst); + } if (machInst.vill) return std::make_shared("VILL is set", machInst); RiscvISA::vreg_t tmp_v0; @@ -1182,6 +1218,12 @@ Fault using vu = std::make_unsigned_t; Fault fault = NoFault; Addr EA; + MISA misa = xc->readMiscReg(MISCREG_ISA); + STATUS status = xc->readMiscReg(MISCREG_STATUS); + if (!misa.rvv || status.vs == VPUStatus::OFF) { + return std::make_shared( + "RVV is disabled or VPU is off", machInst); + } if (machInst.vill) return std::make_shared("VILL is set", machInst); %(op_src_decl)s; @@ -1382,6 +1424,12 @@ Fault using vu = std::make_unsigned_t; Fault fault = NoFault; Addr EA; + MISA misa = xc->readMiscReg(MISCREG_ISA); + STATUS status = xc->readMiscReg(MISCREG_STATUS); + if (!misa.rvv || status.vs == VPUStatus::OFF) { + return std::make_shared( + "RVV is disabled or VPU is off", machInst); + } if (machInst.vill) return std::make_shared("VILL is set", machInst); %(op_src_decl)s;