Remove bus and top level parameters from cache
src/mem/cache/base_cache.hh:
Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
Remove top level parameters from the cache
--HG--
extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
This commit is contained in:
27
src/mem/cache/base_cache.hh
vendored
27
src/mem/cache/base_cache.hh
vendored
@@ -212,10 +212,6 @@ class BaseCache : public MemObject
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protected:
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/** True if this cache is connected to the CPU. */
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bool topLevelCache;
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/** Stores time the cache blocked for statistics. */
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Tick blockedCycle;
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@@ -337,7 +333,7 @@ class BaseCache : public MemObject
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*/
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BaseCache(const std::string &name, Params ¶ms)
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: MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
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slaveRequests(0), topLevelCache(false), blkSize(params.blkSize),
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slaveRequests(0), blkSize(params.blkSize),
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missCount(params.maxMisses)
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{
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//Start ports at null if more than one is created we should panic
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@@ -357,15 +353,6 @@ class BaseCache : public MemObject
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return blkSize;
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}
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/**
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* Returns true if this cache is connect to the CPU.
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* @return True if this is a L1 cache.
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*/
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bool isTopLevel()
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{
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return topLevelCache;
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}
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/**
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* Returns true if the cache is blocked for accesses.
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*/
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@@ -561,8 +548,6 @@ class BaseCache : public MemObject
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*/
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void respondToSnoop(Packet *pkt, Tick time)
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{
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// assert("Implement\n" && 0);
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// mi->respond(pkt,curTick + hitLatency);
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assert (pkt->needsResponse());
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CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
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reqMem->schedule(time);
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@@ -585,15 +570,7 @@ class BaseCache : public MemObject
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{
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//This is where snoops get updated
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AddrRangeList dummy;
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// if (!topLevelCache)
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// {
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cpuSidePort->getPeerAddressRanges(dummy, snoop);
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// }
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// else
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// {
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// snoop.push_back(RangeSize(0,-1));
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// }
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cpuSidePort->getPeerAddressRanges(dummy, snoop);
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return;
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}
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}
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