Remove bus and top level parameters from cache

src/mem/cache/base_cache.hh:
    Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
    Remove top level parameters from the cache

--HG--
extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
This commit is contained in:
Ron Dreslinski
2006-10-12 14:21:25 -04:00
parent f89b56b61a
commit fe230ddb8f
3 changed files with 10 additions and 40 deletions

View File

@@ -212,10 +212,6 @@ class BaseCache : public MemObject
protected:
/** True if this cache is connected to the CPU. */
bool topLevelCache;
/** Stores time the cache blocked for statistics. */
Tick blockedCycle;
@@ -337,7 +333,7 @@ class BaseCache : public MemObject
*/
BaseCache(const std::string &name, Params &params)
: MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
slaveRequests(0), topLevelCache(false), blkSize(params.blkSize),
slaveRequests(0), blkSize(params.blkSize),
missCount(params.maxMisses)
{
//Start ports at null if more than one is created we should panic
@@ -357,15 +353,6 @@ class BaseCache : public MemObject
return blkSize;
}
/**
* Returns true if this cache is connect to the CPU.
* @return True if this is a L1 cache.
*/
bool isTopLevel()
{
return topLevelCache;
}
/**
* Returns true if the cache is blocked for accesses.
*/
@@ -561,8 +548,6 @@ class BaseCache : public MemObject
*/
void respondToSnoop(Packet *pkt, Tick time)
{
// assert("Implement\n" && 0);
// mi->respond(pkt,curTick + hitLatency);
assert (pkt->needsResponse());
CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
reqMem->schedule(time);
@@ -585,15 +570,7 @@ class BaseCache : public MemObject
{
//This is where snoops get updated
AddrRangeList dummy;
// if (!topLevelCache)
// {
cpuSidePort->getPeerAddressRanges(dummy, snoop);
// }
// else
// {
// snoop.push_back(RangeSize(0,-1));
// }
cpuSidePort->getPeerAddressRanges(dummy, snoop);
return;
}
}