derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Some hand merges

Browse Source 
--HG--
rename : objects/BaseCache.mpy => python/m5/objects/BaseCache.mpy
extra : convert_revision : b24ff4c1feb480cf280207d4bbdfe08ef80d1aa2
This commit is contained in:
Ron Dreslinski
2005-04-01 19:39:23 -05:00
parent 9ba57eafc2 c21bf8e7ae
commit fdceb0f00c
3 changed files with 15 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
python/m5/objects/BaseCache.mpy
View File

@@ -36,3 +36,12 @@ simobj BaseCache(BaseMem):
two_queue = Param.Bool(False,
"whether the lifo should have two queue replacement")
write_buffers = Param.Int(8, "number of write buffers")
prefetch_miss = Param.Bool(False,
"wheter you are using the hardware prefetcher from Miss stream")
prefetch_access = Param.Bool(False,
"wheter you are using the hardware prefetcher from Access stream")
prefetcher_size = Param.Int(100,
"Number of entries in the harware prefetch queue")
prefetch_past_page = Param.Bool(False,
"Allow prefetches to cross virtual page boundaries")