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X86: Work on the page table walker, TLB, and related faults.

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--HG--
extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
This commit is contained in:
Gabe Black
2007-11-12 14:38:31 -08:00
parent f17f3d20be
commit fce45baf17
8 changed files with 474 additions and 129 deletions
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4
src/cpu/BaseCPU.py
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@@ -100,7 +100,7 @@ class BaseCPU(SimObject):
_mem_ports = []
if build_env['TARGET_ISA'] == 'x86':
if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
itb.walker_port = Port("ITB page table walker port")
dtb.walker_port = Port("ITB page table walker port")
_mem_ports = ["itb.walker_port", "dtb.walker_port"]
@@ -117,7 +117,7 @@ class BaseCPU(SimObject):
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
if build_env['TARGET_ISA'] == 'x86':
if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c):

2
src/cpu/simple/base.cc
View File

@@ -466,9 +466,9 @@ BaseSimpleCPU::advancePC(Fault fault)
if (fault != NoFault) {
curMacroStaticInst = StaticInst::nullStaticInstPtr;
predecoder.reset();
fault->invoke(tc);
thread->setMicroPC(0);
thread->setNextMicroPC(1);
fault->invoke(tc);
} else {
//If we're at the last micro op for this instruction
if (curStaticInst && curStaticInst->isLastMicroop()) {