From 368fcdde75252db5c79c6bc97a0360f4b150dc82 Mon Sep 17 00:00:00 2001 From: Aditya K Kamath Date: Wed, 22 Nov 2023 20:09:45 +0000 Subject: [PATCH 1/2] arch-x86: Fixes page fault for CLFLUSH on write-protected pages Converts CLFLUSHOPT/WB/FLUSH operations from Write to Read operations during address translation so that they don't trigger a page fault when done on write-protected pages. --- src/arch/x86/tlb.cc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 5ccd3e832d..c7d144bd8a 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -509,6 +509,9 @@ TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) { bool delayedResponse; + // CLFLUSHOPT/WB/FLUSH should be treated as read for protection checks + if (req->isCacheClean()) + mode = BaseMMU::Read; return TLB::translate(req, tc, NULL, mode, delayedResponse, false); } @@ -516,6 +519,9 @@ Fault TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) { + // CLFLUSHOPT/WB/FLUSH should be treated as read for protection checks + if (req->isCacheClean()) + mode = BaseMMU::Read; unsigned logBytes; const Addr vaddr = req->getVaddr(); Addr addr = vaddr; @@ -553,6 +559,9 @@ TLB::translateTiming(const RequestPtr &req, ThreadContext *tc, { bool delayedResponse; assert(translation); + // CLFLUSHOPT/WB/FLUSH should be treated as read for protection checks + if (req->isCacheClean()) + mode = BaseMMU::Read; Fault fault = TLB::translate(req, tc, translation, mode, delayedResponse, true); if (!delayedResponse) From 9a0566e295d54d9748bd91d0ba2a5a618726eafc Mon Sep 17 00:00:00 2001 From: Aditya K Kamath Date: Wed, 22 Nov 2023 20:09:45 +0000 Subject: [PATCH 2/2] arch-x86: Fixes page fault for CLFLUSH on write-protected pages Converts CLFLUSHOPT/WB/FLUSH operations from Write to Read operations during address translation so that they don't trigger a page fault when done on write-protected pages. Change-Id: I20e89cc0cb2b288b36ba1f0ba39a2e1bf0f728af --- src/arch/x86/tlb.cc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 5ccd3e832d..c7d144bd8a 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -509,6 +509,9 @@ TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) { bool delayedResponse; + // CLFLUSHOPT/WB/FLUSH should be treated as read for protection checks + if (req->isCacheClean()) + mode = BaseMMU::Read; return TLB::translate(req, tc, NULL, mode, delayedResponse, false); } @@ -516,6 +519,9 @@ Fault TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) { + // CLFLUSHOPT/WB/FLUSH should be treated as read for protection checks + if (req->isCacheClean()) + mode = BaseMMU::Read; unsigned logBytes; const Addr vaddr = req->getVaddr(); Addr addr = vaddr; @@ -553,6 +559,9 @@ TLB::translateTiming(const RequestPtr &req, ThreadContext *tc, { bool delayedResponse; assert(translation); + // CLFLUSHOPT/WB/FLUSH should be treated as read for protection checks + if (req->isCacheClean()) + mode = BaseMMU::Read; Fault fault = TLB::translate(req, tc, translation, mode, delayedResponse, true); if (!delayedResponse)