From fcb544d569ac3f671cb9ed3a0ee923f4d508abcf Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Thu, 12 Aug 2021 11:46:29 +0100
Subject: [PATCH] arch-arm: Allow the L2 unified TLB to store partial
 translations

We are allowing the L2 TLB to store partial translations from the
second level of lookup

JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: I1286c14a256470c2075fe5533930617139d4d087
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52126
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/arm/ArmMMU.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py
index abf36e0416..a0bbda8dbb 100644
--- a/src/arch/arm/ArmMMU.py
+++ b/src/arch/arm/ArmMMU.py
@@ -65,7 +65,8 @@ class ArmMMU(BaseMMU):
     cxx_header = 'arch/arm/mmu.hh'
 
     # L2 TLBs
-    l2_shared = ArmTLB(entry_type="unified", size=1280)
+    l2_shared = ArmTLB(entry_type="unified", size=1280,
+        partial_levels=["L2"])
 
     # L1 TLBs
     itb = ArmTLB(entry_type="instruction", next_level=Parent.l2_shared)