diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 96c1ec1aef..01f94e4260 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -419,6 +419,7 @@ def operands {{
     'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
     'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
     'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'),
+    'PendingDvm': cntrlRegNC('MISCREG_TLBINEEDSYNC'),
 
     #Register fields for microops
     'URa' : intReg('ura'),