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Backing in more changsets, getting closer to compile

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base_cache.cc compiles, continuing on

src/SConscript:
    Add in compilation flags for cache files
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
    Back in more fixes, now base_cache compiles
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lru.cc:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/request.hh:
    Backing in more changsets, getting closer to compile

--HG--
extra : convert_revision : ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed
This commit is contained in:
Ron Dreslinski
2006-06-28 14:35:00 -04:00
parent ed8564a6b9
commit fc281d0b64
25 changed files with 225 additions and 118 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
src/mem/cache/cache_impl.hh vendored
View File

@@ -175,7 +175,7 @@ Cache<TagStore,Buffering,Coherence>::access(Packet &pkt)
//We are determining prefetches on access stream, call prefetcher
prefetcher->handleMiss(pkt, curTick);
}
if (!pkt->isUncacheable()) {
if (!pkt->req->isUncacheable()) {
if (pkt->cmd.isInvalidate() && !pkt->cmd.isRead()
&& !pkt->cmd.isWrite()) {
//Upgrade or Invalidate
@@ -220,7 +220,7 @@ Cache<TagStore,Buffering,Coherence>::access(Packet &pkt)
pkt->paddr & ~((Addr)blkSize - 1), pkt->pc);
if (blk) {
// Hit
hits[pkt->cmd.toIndex()][pkt->thread_num]++;
hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
// clear dirty bit if write through
if (!pkt->cmd.isNoResponse())
respond(pkt, curTick+lat);
@@ -228,8 +228,8 @@ Cache<TagStore,Buffering,Coherence>::access(Packet &pkt)
}
// Miss
if (!pkt->isUncacheable()) {
misses[pkt->cmd.toIndex()][pkt->thread_num]++;
if (!pkt->req->isUncacheable()) {
misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
/** @todo Move miss count code into BaseCache */
if (missCount) {
--missCount;
@@ -248,8 +248,8 @@ Cache<TagStore,Buffering,Coherence>::getPacket()
{
Packet * pkt = missQueue->getPacket();
if (pkt) {
if (!pkt->isUncacheable()) {
if (pkt->cmd == Hard_Prefetch) misses[Hard_Prefetch][pkt->thread_num]++;
if (!pkt->req->isUncacheable()) {
if (pkt->cmd == Hard_Prefetch) misses[Hard_Prefetch][pkt->req->getThreadNum()]++;
BlkType *blk = tags->findBlock(pkt);
Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
(blk)? blk->status : 0);
@@ -272,7 +272,7 @@ Cache<TagStore,Buffering,Coherence>::sendResult(MemPktPtr &pkt, bool success)
if (pkt->cmd == Upgrade) {
handleResponse(pkt);
}
} else if (pkt && !pkt->isUncacheable()) {
} else if (pkt && !pkt->req->isUncacheable()) {
missQueue->restoreOrigCmd(pkt);
}
}
@@ -394,7 +394,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
for (int i=0; i<writebacks.size(); i++) {
mshr = writebacks[i];
if (!mshr->pkt->isUncacheable()) {
if (!mshr->pkt->req->isUncacheable()) {
if (pkt->cmd.isRead()) {
//Only Upgrades don't get here
//Supply the data
@@ -469,7 +469,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
{
MemDebug::cacheProbe(pkt);
if (!pkt->isUncacheable()) {
if (!pkt->req->isUncacheable()) {
if (pkt->cmd.isInvalidate() && !pkt->cmd.isRead()
&& !pkt->cmd.isWrite()) {
//Upgrade or Invalidate, satisfy it, don't forward
@@ -583,7 +583,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
// Can't handle it, return pktuest unsatisfied.
return 0;
}
if (!pkt->isUncacheable()) {
if (!pkt->req->isUncacheable()) {
// Fetch the cache block to fill
Packet * busPkt = new MemPkt();
busPkt->paddr = blk_addr;
@@ -596,7 +596,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
busPkt->req->asid = pkt->req->asid;
busPkt->xc = pkt->xc;
busPkt->thread_num = pkt->thread_num;
busPkt->req->setThreadNum() = pkt->req->getThreadNum();
busPkt->time = curTick;
lat = mi->sendProbe(busPkt, update);
@@ -606,7 +606,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
return 0;
}
misses[pkt->cmd.toIndex()][pkt->thread_num]++;
misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
CacheBlk::State old_state = (blk) ? blk->status : 0;
tags->handleFill(blk, busPkt,
@@ -631,7 +631,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
}
if (update) {
hits[pkt->cmd.toIndex()][pkt->thread_num]++;
hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
} else if (pkt->cmd.isWrite()) {
// Still need to change data in all locations.
return mi->sendProbe(pkt, update);