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Backing in more changsets, getting closer to compile

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base_cache.cc compiles, continuing on

src/SConscript:
    Add in compilation flags for cache files
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
    Back in more fixes, now base_cache compiles
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lru.cc:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/request.hh:
    Backing in more changsets, getting closer to compile

--HG--
extra : convert_revision : ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed
This commit is contained in:
Ron Dreslinski
2006-06-28 14:35:00 -04:00
parent ed8564a6b9
commit fc281d0b64
25 changed files with 225 additions and 118 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
src/mem/cache/base_cache.cc vendored
View File

@@ -45,11 +45,11 @@ BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
{
blocked = false;
//Start ports at null if more than one is created we should panic
cpuSidePort = NULL;
memSidePort = NULL;
//cpuSidePort = NULL;
//memSidePort = NULL;
}
bool
void
BaseCache::CachePort::recvStatusChange(Port::Status status)
{
cache->recvStatusChange(status, isCpuSide);
@@ -121,12 +121,16 @@ BaseCache::getPort(const std::string &if_name)
void
BaseCache::regStats()
{
Request temp_req;
Packet::Command temp_cmd = Packet::ReadReq;
Packet temp_pkt(&temp_req, temp_cmd, 0); //@todo FIx command strings so this isn't neccessary
using namespace Stats;
// Hit statistics
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
Packet::Command cmd = (Packet::CommandEnum)access_idx;
const string &cstr = cmd.toString();
Packet::Command cmd = (Packet::Command)access_idx;
const string &cstr = temp_pkt.cmdIdxToString(cmd);
hits[access_idx]
.init(maxThreadsPerCPU)
@@ -141,20 +145,20 @@ BaseCache::regStats()
.desc("number of demand (read+write) hits")
.flags(total)
;
demandHits = hits[Read] + hits[Write];
demandHits = hits[Packet::ReadReq] + hits[Packet::WriteReq];
overallHits
.name(name() + ".overall_hits")
.desc("number of overall hits")
.flags(total)
;
overallHits = demandHits + hits[Soft_Prefetch] + hits[Hard_Prefetch]
+ hits[Writeback];
overallHits = demandHits + hits[Packet::SoftPFReq] + hits[Packet::HardPFReq]
+ hits[Packet::Writeback];
// Miss statistics
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
Packet::Command cmd = (Packet::CommandEnum)access_idx;
const string &cstr = cmd.toString();
Packet::Command cmd = (Packet::Command)access_idx;
const string &cstr = temp_pkt.cmdIdxToString(cmd);
misses[access_idx]
.init(maxThreadsPerCPU)
@@ -169,20 +173,20 @@ BaseCache::regStats()
.desc("number of demand (read+write) misses")
.flags(total)
;
demandMisses = misses[Read] + misses[Write];
demandMisses = misses[Packet::ReadReq] + misses[Packet::WriteReq];
overallMisses
.name(name() + ".overall_misses")
.desc("number of overall misses")
.flags(total)
;
overallMisses = demandMisses + misses[Soft_Prefetch] +
misses[Hard_Prefetch] + misses[Writeback];
overallMisses = demandMisses + misses[Packet::SoftPFReq] +
misses[Packet::HardPFReq] + misses[Packet::Writeback];
// Miss latency statistics
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
Packet::Command cmd = (Packet::CommandEnum)access_idx;
const string &cstr = cmd.toString();
Packet::Command cmd = (Packet::Command)access_idx;
const string &cstr = temp_pkt.cmdIdxToString(cmd);
missLatency[access_idx]
.init(maxThreadsPerCPU)
@@ -197,20 +201,20 @@ BaseCache::regStats()
.desc("number of demand (read+write) miss cycles")
.flags(total)
;
demandMissLatency = missLatency[Read] + missLatency[Write];
demandMissLatency = missLatency[Packet::ReadReq] + missLatency[Packet::WriteReq];
overallMissLatency
.name(name() + ".overall_miss_latency")
.desc("number of overall miss cycles")
.flags(total)
;
overallMissLatency = demandMissLatency + missLatency[Soft_Prefetch] +
missLatency[Hard_Prefetch];
overallMissLatency = demandMissLatency + missLatency[Packet::SoftPFReq] +
missLatency[Packet::HardPFReq];
// access formulas
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
Packet::Command cmd = (Packet::CommandEnum)access_idx;
const string &cstr = cmd.toString();
Packet::Command cmd = (Packet::Command)access_idx;
const string &cstr = temp_pkt.cmdIdxToString(cmd);
accesses[access_idx]
.name(name() + "." + cstr + "_accesses")
@@ -237,8 +241,8 @@ BaseCache::regStats()
// miss rate formulas
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
Packet::Command cmd = (Packet::CommandEnum)access_idx;
const string &cstr = cmd.toString();
Packet::Command cmd = (Packet::Command)access_idx;
const string &cstr = temp_pkt.cmdIdxToString(cmd);
missRate[access_idx]
.name(name() + "." + cstr + "_miss_rate")
@@ -265,8 +269,8 @@ BaseCache::regStats()
// miss latency formulas
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
Packet::Command cmd = (Packet::CommandEnum)access_idx;
const string &cstr = cmd.toString();
Packet::Command cmd = (Packet::Command)access_idx;
const string &cstr = temp_pkt.cmdIdxToString(cmd);
avgMissLatency[access_idx]
.name(name() + "." + cstr + "_avg_miss_latency")