From fb663678e619f485bb467be77764021414626735 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 24 Jan 2021 16:39:49 -0800 Subject: [PATCH] base,cpu,sim: Stop "using namespace TheISA". This was mostly not used to begin with, but also when it was used, it would obscure places where there were types, functions, etc, which were switched between ISAs at compile time, and which would need to be cleaned up to allow more than one ISA at a time. Change-Id: Ieb372feff91b7e946b477fb78e54bcd0c2138966 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39655 Reviewed-by: Bobby R. Bruce Reviewed-by: Daniel Carvalho Maintainer: Bobby R. Bruce Tested-by: kokoro --- src/base/remote_gdb.cc | 4 +-- src/cpu/checker/cpu.cc | 2 -- src/cpu/checker/cpu_impl.hh | 4 +-- src/cpu/exetrace.cc | 4 +-- src/cpu/inteltrace.cc | 2 -- src/cpu/o3/cpu.cc | 2 -- src/cpu/o3/lsq_unit_impl.hh | 2 -- src/cpu/simple/atomic.cc | 2 -- src/cpu/simple/base.cc | 8 ++--- src/cpu/simple/timing.cc | 2 -- src/cpu/thread_context.cc | 64 ++++++++++++++++++------------------- src/sim/process.cc | 2 -- src/sim/syscall_emul.cc | 2 -- src/sim/system.cc | 14 ++++---- 14 files changed, 43 insertions(+), 71 deletions(-) diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc index 0c1215e7ac..1e86a693f1 100644 --- a/src/base/remote_gdb.cc +++ b/src/base/remote_gdb.cc @@ -151,8 +151,6 @@ #include "sim/full_system.hh" #include "sim/system.hh" -using namespace TheISA; - static const char GDBStart = '$'; static const char GDBEnd = '#'; static const char GDBGoodP = '+'; @@ -803,7 +801,7 @@ std::map BaseRemoteGDB::command_map = { bool BaseRemoteGDB::checkBpLen(size_t len) { - return len == sizeof(MachInst); + return len == sizeof(TheISA::MachInst); } bool diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index 8815530b51..a9baf88521 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -52,8 +52,6 @@ #include "params/CheckerCPU.hh" #include "sim/full_system.hh" -using namespace TheISA; - void CheckerCPU::init() { diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 733cf1c1c2..7fe05c6551 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -59,8 +59,6 @@ #include "sim/sim_object.hh" #include "sim/stats.hh" -using namespace TheISA; - template void Checker::advancePC(const Fault &fault) @@ -200,7 +198,7 @@ Checker::verify(const DynInstPtr &completed_inst) Fault fault = NoFault; // maintain $r0 semantics - thread->setIntReg(ZeroReg, 0); + thread->setIntReg(TheISA::ZeroReg, 0); // Check if any recent PC changes match up with anything we // expect to happen. This is mostly to check if traps or diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 02ede1a0cd..7bf60e7489 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -53,8 +53,6 @@ #include "debug/FmtTicksOff.hh" #include "enums/OpClass.hh" -using namespace TheISA; - namespace Trace { void @@ -77,7 +75,7 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran) Addr cur_pc = pc.instAddr(); Loader::SymbolTable::const_iterator it; ccprintf(outs, "%#x", cur_pc); - if (Debug::ExecSymbol && (!FullSystem || !inUserMode(thread)) && + if (Debug::ExecSymbol && (!FullSystem || !TheISA::inUserMode(thread)) && (it = Loader::debugSymbolTable.findNearest(cur_pc)) != Loader::debugSymbolTable.end()) { Addr delta = cur_pc - it->address; diff --git a/src/cpu/inteltrace.cc b/src/cpu/inteltrace.cc index 4e36a9d1ff..2212dbf383 100644 --- a/src/cpu/inteltrace.cc +++ b/src/cpu/inteltrace.cc @@ -34,8 +34,6 @@ #include "cpu/exetrace.hh" #include "cpu/static_inst.hh" -using namespace TheISA; - namespace Trace { void diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 56cf46c1ed..c84f89bc07 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -64,8 +64,6 @@ struct BaseCPUParams; -using namespace TheISA; - BaseO3CPU::BaseO3CPU(const BaseCPUParams ¶ms) : BaseCPU(params) { diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 2c6a16cadd..d8114801b9 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -610,7 +610,6 @@ template Fault LSQUnit::executeLoad(const DynInstPtr &inst) { - using namespace TheISA; // Execute a specific load. Fault load_fault = NoFault; @@ -678,7 +677,6 @@ template Fault LSQUnit::executeStore(const DynInstPtr &store_inst) { - using namespace TheISA; // Make sure that a store exists. assert(stores != 0); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index ae4ffec674..f0c276bb1f 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -58,8 +58,6 @@ #include "sim/full_system.hh" #include "sim/system.hh" -using namespace TheISA; - void AtomicSimpleCPU::init() { diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 113f8e6564..62df848812 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -77,8 +77,6 @@ #include "sim/stats.hh" #include "sim/system.hh" -using namespace TheISA; - BaseSimpleCPU::BaseSimpleCPU(const BaseSimpleCPUParams &p) : BaseCPU(p), curThread(0), @@ -298,7 +296,7 @@ BaseSimpleCPU::setupFetchRequest(const RequestPtr &req) // set up memory request for instruction fetch DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC); - req->setVirt(fetchPC, sizeof(MachInst), Request::INST_FETCH, + req->setVirt(fetchPC, sizeof(TheISA::MachInst), Request::INST_FETCH, instRequestorId(), instAddr); } @@ -310,7 +308,7 @@ BaseSimpleCPU::preExecute() SimpleThread* thread = t_info.thread; // maintain $r0 semantics - thread->setIntReg(ZeroReg, 0); + thread->setIntReg(TheISA::ZeroReg, 0); // resets predicates t_info.setPredicate(true); @@ -348,7 +346,7 @@ BaseSimpleCPU::preExecute() thread->pcState(pcState); } else { t_info.stayAtPC = true; - t_info.fetchOffset += sizeof(MachInst); + t_info.fetchOffset += sizeof(TheISA::MachInst); } //If we decoded an instruction and it's microcoded, start pulling diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index aaabda56a1..3109f8a183 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -58,8 +58,6 @@ #include "sim/full_system.hh" #include "sim/system.hh" -using namespace TheISA; - void TimingSimpleCPU::init() { diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc index d1d89df14a..16db818ade 100644 --- a/src/cpu/thread_context.cc +++ b/src/cpu/thread_context.cc @@ -141,37 +141,36 @@ ThreadContext::quiesceTick(Tick resume) void serialize(const ThreadContext &tc, CheckpointOut &cp) { - using namespace TheISA; - - RegVal floatRegs[NumFloatRegs]; - for (int i = 0; i < NumFloatRegs; ++i) + RegVal floatRegs[TheISA::NumFloatRegs]; + for (int i = 0; i < TheISA::NumFloatRegs; ++i) floatRegs[i] = tc.readFloatRegFlat(i); // This is a bit ugly, but needed to maintain backwards // compatibility. - arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs); + arrayParamOut(cp, "floatRegs.i", floatRegs, TheISA::NumFloatRegs); - std::vector vecRegs(NumVecRegs); - for (int i = 0; i < NumVecRegs; ++i) { + std::vector vecRegs(TheISA::NumVecRegs); + for (int i = 0; i < TheISA::NumVecRegs; ++i) { vecRegs[i] = tc.readVecRegFlat(i); } SERIALIZE_CONTAINER(vecRegs); - std::vector vecPredRegs(NumVecPredRegs); - for (int i = 0; i < NumVecPredRegs; ++i) { + std::vector + vecPredRegs(TheISA::NumVecPredRegs); + for (int i = 0; i < TheISA::NumVecPredRegs; ++i) { vecPredRegs[i] = tc.readVecPredRegFlat(i); } SERIALIZE_CONTAINER(vecPredRegs); - RegVal intRegs[NumIntRegs]; - for (int i = 0; i < NumIntRegs; ++i) + RegVal intRegs[TheISA::NumIntRegs]; + for (int i = 0; i < TheISA::NumIntRegs; ++i) intRegs[i] = tc.readIntRegFlat(i); - SERIALIZE_ARRAY(intRegs, NumIntRegs); + SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); - if (NumCCRegs) { - RegVal ccRegs[NumCCRegs]; - for (int i = 0; i < NumCCRegs; ++i) + if (TheISA::NumCCRegs) { + RegVal ccRegs[TheISA::NumCCRegs]; + for (int i = 0; i < TheISA::NumCCRegs; ++i) ccRegs[i] = tc.readCCRegFlat(i); - SERIALIZE_ARRAY(ccRegs, NumCCRegs); + SERIALIZE_ARRAY(ccRegs, TheISA::NumCCRegs); } tc.pcState().serialize(cp); @@ -182,40 +181,39 @@ serialize(const ThreadContext &tc, CheckpointOut &cp) void unserialize(ThreadContext &tc, CheckpointIn &cp) { - using namespace TheISA; - - RegVal floatRegs[NumFloatRegs]; + RegVal floatRegs[TheISA::NumFloatRegs]; // This is a bit ugly, but needed to maintain backwards // compatibility. - arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs); - for (int i = 0; i < NumFloatRegs; ++i) + arrayParamIn(cp, "floatRegs.i", floatRegs, TheISA::NumFloatRegs); + for (int i = 0; i < TheISA::NumFloatRegs; ++i) tc.setFloatRegFlat(i, floatRegs[i]); - std::vector vecRegs(NumVecRegs); + std::vector vecRegs(TheISA::NumVecRegs); UNSERIALIZE_CONTAINER(vecRegs); - for (int i = 0; i < NumVecRegs; ++i) { + for (int i = 0; i < TheISA::NumVecRegs; ++i) { tc.setVecRegFlat(i, vecRegs[i]); } - std::vector vecPredRegs(NumVecPredRegs); + std::vector + vecPredRegs(TheISA::NumVecPredRegs); UNSERIALIZE_CONTAINER(vecPredRegs); - for (int i = 0; i < NumVecPredRegs; ++i) { + for (int i = 0; i < TheISA::NumVecPredRegs; ++i) { tc.setVecPredRegFlat(i, vecPredRegs[i]); } - RegVal intRegs[NumIntRegs]; - UNSERIALIZE_ARRAY(intRegs, NumIntRegs); - for (int i = 0; i < NumIntRegs; ++i) + RegVal intRegs[TheISA::NumIntRegs]; + UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); + for (int i = 0; i < TheISA::NumIntRegs; ++i) tc.setIntRegFlat(i, intRegs[i]); - if (NumCCRegs) { - RegVal ccRegs[NumCCRegs]; - UNSERIALIZE_ARRAY(ccRegs, NumCCRegs); - for (int i = 0; i < NumCCRegs; ++i) + if (TheISA::NumCCRegs) { + RegVal ccRegs[TheISA::NumCCRegs]; + UNSERIALIZE_ARRAY(ccRegs, TheISA::NumCCRegs); + for (int i = 0; i < TheISA::NumCCRegs; ++i) tc.setCCRegFlat(i, ccRegs[i]); } - PCState pcState; + TheISA::PCState pcState; pcState.unserialize(cp); tc.pcState(pcState); diff --git a/src/sim/process.cc b/src/sim/process.cc index 1ae8d4096b..21d4c2ad28 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -67,8 +67,6 @@ #include "sim/syscall_desc.hh" #include "sim/system.hh" -using namespace TheISA; - namespace { diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc index c85d893173..8f04cd538a 100644 --- a/src/sim/syscall_emul.cc +++ b/src/sim/syscall_emul.cc @@ -53,8 +53,6 @@ #include "sim/syscall_desc.hh" #include "sim/system.hh" -using namespace TheISA; - void warnUnsupportedOS(std::string syscall_name) { diff --git a/src/sim/system.cc b/src/sim/system.cc index f2f10bc823..bb3c0beea3 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -71,8 +71,6 @@ #include "sim/full_system.hh" #include "sim/redirect_path.hh" -using namespace TheISA; - std::vector System::systemList; void @@ -128,7 +126,7 @@ System::Threads::insert(ThreadContext *tc, ContextID id) # if THE_ISA != NULL_ISA int port = getRemoteGDBPort(); if (port) { - t.gdb = new RemoteGDB(sys, tc, port + id); + t.gdb = new TheISA::RemoteGDB(sys, tc, port + id); t.gdb->listen(); } # endif @@ -378,18 +376,18 @@ System::validKvmEnvironment() const Addr System::allocPhysPages(int npages) { - Addr return_addr = pagePtr << PageShift; + Addr return_addr = pagePtr << TheISA::PageShift; pagePtr += npages; - Addr next_return_addr = pagePtr << PageShift; + Addr next_return_addr = pagePtr << TheISA::PageShift; if (_m5opRange.contains(next_return_addr)) { warn("Reached m5ops MMIO region\n"); return_addr = 0xffffffff; - pagePtr = 0xffffffff >> PageShift; + pagePtr = 0xffffffff >> TheISA::PageShift; } - if ((pagePtr << PageShift) > physmem.totalSize()) + if ((pagePtr << TheISA::PageShift) > physmem.totalSize()) fatal("Out of memory, please increase size of physical memory."); return return_addr; } @@ -403,7 +401,7 @@ System::memSize() const Addr System::freeMemSize() const { - return physmem.totalSize() - (pagePtr << PageShift); + return physmem.totalSize() - (pagePtr << TheISA::PageShift); } bool