From f95e1505b839a95489bf3cfa6cec9833781bf788 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 13 Sep 2023 13:36:33 +0100 Subject: [PATCH] util: Fix TLM configs making use of TraceCPU replayer A recent PR [1] moved the TraceCPU away from the BaseCPU hierarchy. While the common etrace_replayer.py has been amended, I missed these hybrid TLM + TraceCPU example scripts. [1]: https://github.com/gem5/gem5/pull/302 Change-Id: I7e9bc9a612d2721d72f5881ddb2fb4d9ee011587 Signed-off-by: Giacomo Travaglini --- util/tlm/conf/tlm_elastic_slave.py | 13 ++++++------- util/tlm/examples/tlm_elastic_slave_with_l2.py | 17 ++++++++--------- 2 files changed, 14 insertions(+), 16 deletions(-) diff --git a/util/tlm/conf/tlm_elastic_slave.py b/util/tlm/conf/tlm_elastic_slave.py index 30a412b2f8..1007c5244b 100644 --- a/util/tlm/conf/tlm_elastic_slave.py +++ b/util/tlm/conf/tlm_elastic_slave.py @@ -65,7 +65,7 @@ from Caches import * # Setup System: system = System( - cpu=TraceCPU(cpu_id=0), + cpu=TraceCPU(), mem_mode="timing", mem_ranges=[AddrRange("512MB")], cache_line_size=64, @@ -89,8 +89,7 @@ system.cpu_clk_domain = SrcClockDomain( clock="1GHz", voltage_domain=system.cpu_voltage_domain ) -# Setup CPU and its L1 caches: -system.cpu.createInterruptController() +# Setup CPU's L1 caches: system.cpu.icache = L1_ICache(size="32kB") system.cpu.dcache = L1_DCache(size="32kB") system.cpu.icache.cpu_side = system.cpu.icache_port @@ -114,10 +113,10 @@ system.tlm.port_data = "transactor" # Connect everything: system.membus = SystemXBar() -system.system_port = system.membus.slave -system.cpu.icache.mem_side = system.membus.slave -system.cpu.dcache.mem_side = system.membus.slave -system.membus.master = system.tlm.port +system.system_port = system.membus.cpu_side_ports +system.cpu.icache.mem_side = system.membus.cpu_side_ports +system.cpu.dcache.mem_side = system.membus.cpu_side_ports +system.membus.mem_side_ports = system.tlm.port # Start the simulation: root = Root(full_system=False, system=system) diff --git a/util/tlm/examples/tlm_elastic_slave_with_l2.py b/util/tlm/examples/tlm_elastic_slave_with_l2.py index c72bc8976c..6b3f7b43fb 100644 --- a/util/tlm/examples/tlm_elastic_slave_with_l2.py +++ b/util/tlm/examples/tlm_elastic_slave_with_l2.py @@ -72,7 +72,7 @@ from Caches import * # Setup System: system = System( - cpu=TraceCPU(cpu_id=0), + cpu=TraceCPU(), mem_mode="timing", mem_ranges=[AddrRange("1024MB")], cache_line_size=64, @@ -96,8 +96,7 @@ system.cpu_clk_domain = SrcClockDomain( clock="1GHz", voltage_domain=system.cpu_voltage_domain ) -# Setup CPU and its L1 caches: -system.cpu.createInterruptController() +# Setup CPU's L1 caches: system.cpu.icache = L1_ICache(size="32kB") system.cpu.dcache = L1_DCache(size="32kB") system.cpu.icache.cpu_side = system.cpu.icache_port @@ -122,12 +121,12 @@ system.tlm.port_data = "transactor1" # Connect everything: system.membus = SystemXBar() -system.system_port = system.membus.slave -system.cpu.icache.mem_side = system.tol2bus.slave -system.cpu.dcache.mem_side = system.tol2bus.slave -system.tol2bus.master = system.l2cache.cpu_side -system.l2cache.mem_side = system.membus.slave -system.membus.master = system.tlm.port +system.system_port = system.membus.cpu_side_ports +system.cpu.icache.mem_side = system.tol2bus.cpu_side_ports +system.cpu.dcache.mem_side = system.tol2bus.cpu_side_ports +system.tol2bus.mem_side_ports = system.l2cache.cpu_side +system.l2cache.mem_side = system.membus.cpu_side_ports +system.membus.mem_side_ports = system.tlm.port # Start the simulation: root = Root(full_system=False, system=system)