diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
index 9404edf1dc..6530854242 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -29,7 +29,7 @@ from m5.SimObject import SimObject
 
 from m5.objects.ArmInterrupts import ArmInterrupts
 from m5.objects.ArmISA import ArmISA
-from m5.objects.FastModel import AmbaInitiatorSocket
+from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
 from m5.objects.IntPin import VectorIntSinkPin
 from m5.objects.Iris import IrisBaseCPU
 from m5.objects.SystemC import SystemC_ScModule
@@ -107,6 +107,8 @@ class FastModelCortexR52Cluster(SimObject):
 
     spi = VectorIntSinkPin('SPI inputs (0-959)')
 
+    ext_slave = AmbaTargetSocket(64, 'AMBA target socket')
+
     CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
             "CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")
     DBGROMADDR = Param.UInt32(0, "Equivalent to CFGDBGROMADDR")
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
index 4f14e7ef33..35e4e079d6 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -150,6 +150,9 @@ CortexR52Cluster::getPort(const std::string &if_name, PortID idx)
 {
     if (if_name == "spi") {
         return evs->gem5_getPort(if_name, idx);
+    } else if (if_name == "ext_slave") {
+        assert(idx == InvalidPortID);
+        return evs->gem5_getPort(if_name, idx);
     } else {
         return SimObject::getPort(if_name, idx);
     }
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc b/src/arch/arm/fastmodel/CortexR52/evs.cc
index 90612ae9d5..f4e091ebbe 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -81,7 +81,8 @@ template <class Types>
 ScxEvsCortexR52<Types>::ScxEvsCortexR52(
         const sc_core::sc_module_name &mod_name, const Params &p) :
     Base(mod_name),
-    params(p)
+    params(p),
+    ext_slave(Base::ext_slave, p.name + ".ext_slave", -1)
 {
     for (int i = 0; i < CoreCount; i++)
         corePins.emplace_back(new CorePins(this, i));
@@ -115,6 +116,8 @@ ScxEvsCortexR52<Types>::gem5_getPort(const std::string &if_name, int idx)
         return this->corePins.at(idx)->flash;
     } else if (if_name == "amba") {
         return this->corePins.at(idx)->amba;
+    } else if (if_name == "ext_slave") {
+        return this->ext_slave;
     } else if (if_name == "spi") {
         return *this->spis.at(idx);
     } else if (if_name.substr(0, 3) == "ppi") {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh b/src/arch/arm/fastmodel/CortexR52/evs.hh
index b27e7e2dbd..d0c1253b37 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -114,6 +114,8 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs
 
     const Params &params;
 
+    AmbaTarget ext_slave;
+
   public:
     ScxEvsCortexR52(const Params &p) : ScxEvsCortexR52(p.name.c_str(), p) {}
     ScxEvsCortexR52(const sc_core::sc_module_name &mod_name, const Params &p);
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
index 9ed73a6570..720d66f3f7 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
@@ -44,6 +44,7 @@ component CortexR52x1
         core.llpp_m => self.llpp;
         core.flash_m => self.flash;
         core.pvbus_core_m => self.amba;
+        self.ext_slave => core.ext_slave_s;
 
         // Clocks.
         clock1Hz.clk_out => clockDiv.clk_in;
@@ -64,6 +65,7 @@ component CortexR52x1
     master port<PVBus> llpp[1];
     master port<PVBus> flash[1];
     master port<PVBus> amba[1];
+    slave port<PVBus> ext_slave;
 
     slave port<ExportedClockRateControl> clock_rate_s
     {
diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
index 147d2e9288..bcbf1f4538 100644
--- a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
@@ -44,6 +44,7 @@ component CortexR52x2
         core.llpp_m => self.llpp;
         core.flash_m => self.flash;
         core.pvbus_core_m => self.amba;
+        self.ext_slave => core.ext_slave_s;
 
         // Clocks.
         clock1Hz.clk_out => clockDiv.clk_in;
@@ -65,6 +66,7 @@ component CortexR52x2
     master port<PVBus> llpp[2];
     master port<PVBus> flash[2];
     master port<PVBus> amba[2];
+    slave port<PVBus> ext_slave;
 
     slave port<ExportedClockRateControl> clock_rate_s
     {
diff --git a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
index 505c5e3e19..3d63bbfc25 100644
--- a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
@@ -44,6 +44,7 @@ component CortexR52x3
         core.llpp_m => self.llpp;
         core.flash_m => self.flash;
         core.pvbus_core_m => self.amba;
+        self.ext_slave => core.ext_slave_s;
 
         // Clocks.
         clock1Hz.clk_out => clockDiv.clk_in;
@@ -66,6 +67,7 @@ component CortexR52x3
     master port<PVBus> llpp[3];
     master port<PVBus> flash[3];
     master port<PVBus> amba[3];
+    slave port<PVBus> ext_slave;
 
     slave port<ExportedClockRateControl> clock_rate_s
     {
diff --git a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
index 00e6522b41..6443383f7f 100644
--- a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
@@ -44,6 +44,7 @@ component CortexR52x4
         core.llpp_m => self.llpp;
         core.flash_m => self.flash;
         core.pvbus_core_m => self.amba;
+        self.ext_slave => core.ext_slave_s;
 
         // Clocks.
         clock1Hz.clk_out => clockDiv.clk_in;
@@ -67,6 +68,7 @@ component CortexR52x4
     master port<PVBus> llpp[4];
     master port<PVBus> flash[4];
     master port<PVBus> amba[4];
+    slave port<PVBus> ext_slave;
 
     slave port<ExportedClockRateControl> clock_rate_s
     {