Merge gblack@m5.eecs.umich.edu:/bk/multiarch

into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 0b3ffc0605c9043d7f5bf6c15f4a3c68846a732a

dev/pktfifo.cc

@@ -31,6 +31,36 @@
 
 using namespace std;
 
+bool
+PacketFifo::copyout(void *dest, int offset, int len)
+{
+    char *data = (char *)dest;
+    if (offset + len >= size())
+        return false;
+
+    list<PacketPtr>::iterator p = fifo.begin();
+    list<PacketPtr>::iterator end = fifo.end();
+    while (len > 0) {
+        while (offset >= (*p)->length) {
+            offset -= (*p)->length;
+            ++p;
+        }
+
+        if (p == end)
+            panic("invalid fifo");
+
+        int size = min((*p)->length - offset, len);
+        memcpy(data, (*p)->data, size);
+        offset = 0;
+        len -= size;
+        data += size;
+        ++p;
+    }
+
+    return true;
+}
+
+
 void
 PacketFifo::serialize(const string &base, ostream &os)
 {
@@ -40,8 +70,8 @@ PacketFifo::serialize(const string &base, ostream &os)
     paramOut(os, base + ".packets", fifo.size());
 
     int i = 0;
-    std::list<PacketPtr>::iterator p = fifo.begin();
-    std::list<PacketPtr>::iterator end = fifo.end();
+    list<PacketPtr>::iterator p = fifo.begin();
+    list<PacketPtr>::iterator end = fifo.end();
     while (p != end) {
         (*p)->serialize(csprintf("%s.packet%d", base, i), os);
         ++p;

dev/pktfifo.hh

@@ -127,6 +127,35 @@ class PacketFifo
         fifo.erase(i);
     }
 
+    bool copyout(void *dest, int offset, int len);
+
+    int countPacketsBefore(iterator end)
+    {
+        iterator i = fifo.begin();
+        int count = 0;
+
+        while (i != end) {
+            ++count;
+            ++i;
+        }
+
+        return count;
+    }
+
+    int countPacketsAfter(iterator i)
+    {
+        iterator end = fifo.end();
+        int count = 0;
+
+        while (i != end) {
+            ++count;
+            ++i;
+        }
+
+        return count;
+    }
+
+
 /**
  * Serialization stuff
  */

dev/sinic.hh

@@ -280,7 +280,6 @@ class Device : public Base
     Fault iprRead(Addr daddr, int cpu, uint64_t &result);
     Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
     Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
-    void regWrite(Addr daddr, int cpu, const uint8_t *data);
     Tick cacheAccess(MemReqPtr &req);
 
 /**