Merge zizzer.eecs.umich.edu:/bk/newmem/

into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : dc165840841bdd88e40111b98d1be493441703f0

src/SConscript

@@ -374,8 +374,15 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
     envList.append(newEnv)
 
 # Debug binary
+# Solaris seems to have some issue with DWARF2 debugging information, it's ok
+# with stabs though
+if sys.platform == 'sunos5':
+   debug_flag = '-gstabs+'
+else:
+   debug_flag = '-ggdb3'
+
 makeEnv('debug', '.do',
-        CCFLAGS = Split('-g3 -gdwarf-2 -O0'),
+        CCFLAGS = Split('%s -O0' % debug_flag),
         CPPDEFINES = 'DEBUG')
 
 # Optimized binary

src/base/statistics.hh

@@ -696,7 +696,7 @@ class ScalarBase : public DataAccess
 
   protected:
     /** The storage of this stat. */
-    char storage[sizeof(Storage)];
+    char storage[sizeof(Storage)] __attribute__ ((aligned (8)));
 
     /** The parameters for this stat. */
     Params params;
@@ -1637,7 +1637,7 @@ class DistBase : public DataAccess
 
   protected:
     /** The storage for this stat. */
-    char storage[sizeof(Storage)];
+    char storage[sizeof(Storage)] __attribute__ ((aligned (8)));
 
     /** The parameters for this stat. */
     Params params;

src/cpu/exetrace.cc

@@ -33,6 +33,8 @@
 
 #include <fstream>
 #include <iomanip>
+#include <sys/ipc.h>
+#include <sys/shm.h>
 
 #include "arch/regfile.hh"
 #include "base/loader/symtab.hh"
@@ -44,10 +46,15 @@
 
 //XXX This is temporary
 #include "arch/isa_specific.hh"
+#include "cpu/m5legion_interface.h"
 
 using namespace std;
 using namespace TheISA;
 
+namespace Trace {
+SharedData *shared_data = NULL;
+}
+
 ////////////////////////////////////////////////////////////////////////
 //
 //  Methods for the InstRecord object
@@ -60,6 +67,7 @@ Trace::InstRecord::dump(ostream &outs)
     if (flags[PRINT_REG_DELTA])
     {
 #if THE_ISA == SPARC_ISA
+#if 0
         //Don't print what happens for each micro-op, just print out
         //once at the last op, and for regular instructions.
         if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
@@ -120,6 +128,7 @@ Trace::InstRecord::dump(ostream &outs)
             }
             outs << endl;
         }
+#endif
 #endif
     }
     else if (flags[INTEL_FORMAT]) {
@@ -222,6 +231,65 @@ Trace::InstRecord::dump(ostream &outs)
         //
         outs << endl;
     }
+    // Compare
+    if (flags[LEGION_LOCKSTEP])
+    {
+        bool compared = false;
+        bool diffPC   = false;
+        bool diffInst = false;
+        bool diffRegs = false;
+
+        while (!compared) {
+            if (shared_data->flags == OWN_M5) {
+                if (shared_data->pc != PC)
+                   diffPC = true;
+                if (shared_data->instruction != staticInst->machInst)
+                    diffInst = true;
+                for (int i = 0; i < TheISA::NumIntRegs; i++) {
+                    if (thread->readIntReg(i) != shared_data->intregs[i])
+                        diffRegs = true;
+                }
+
+                if (diffPC || diffInst || diffRegs ) {
+                    outs << "Differences found between M5 and Legion:";
+                    if (diffPC)
+                        outs << " PC";
+                    if (diffInst)
+                        outs << " Instruction";
+                    if (diffRegs)
+                        outs << " IntRegs";
+                    outs << endl;
+
+                    outs << "M5 PC: " << setw(20) << "0x" << hex << PC;
+                    outs << "Legion PC: " << setw(20) << "0x" << hex <<
+                        shared_data->pc << endl;
+
+
+
+                    outs << "M5 Instruction: " << staticInst->machInst << "("
+                         << staticInst->disassemble(PC, debugSymbolTable)
+                         << ")" << "Legion Instruction: " <<
+                         shared_data->instruction << "("
+                         /*<< legionInst->disassemble(shared_data->pc,
+                                 debugSymbolTable)*/
+                         << ")" << endl;
+
+                    for (int i = 0; i < TheISA::NumIntRegs; i++) {
+                        outs << setw(16) << "0x" << hex << thread->readIntReg(i)
+                             << setw(16) << "0x" << hex << shared_data->intregs[i];
+
+                        if (thread->readIntReg(i) != shared_data->intregs[i])
+                            outs << "<--- Different";
+                        outs << endl;
+                    }
+                }
+
+                compared = true;
+                shared_data->flags = OWN_LEGION;
+            }
+        }
+
+    }
 }
 
 
@@ -271,6 +339,9 @@ Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
                                   "Use symbols for the PC if available", true);
 Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
                                    "print trace in intel compatible format", false);
+Param<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep",
+                                   "Compare sim state to legion state every cycle",
+                                   false);
 Param<string> exe_trace_system(&exeTraceParams, "trace_system",
                                    "print trace of which system (client or server)",
                                    "client");
@@ -296,7 +367,28 @@ Trace::InstRecord::setParams()
     flags[PRINT_REG_DELTA]   = exe_trace_print_reg_delta;
     flags[PC_SYMBOL]         = exe_trace_pc_symbol;
     flags[INTEL_FORMAT]      = exe_trace_intel_format;
+    flags[LEGION_LOCKSTEP]   = exe_trace_legion_lockstep;
     trace_system	     = exe_trace_system;
+
+    // If were going to be in lockstep with Legion
+    // Setup shared memory, and get otherwise ready
+    if (flags[LEGION_LOCKSTEP]) {
+        int shmfd = shmget(getuid(), sizeof(SharedData), 0777);
+        if (shmfd < 0)
+            fatal("Couldn't get shared memory fd. Is Legion running?");
+
+        shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
+        if (shared_data == (SharedData*)-1)
+            fatal("Couldn't allocate shared memory");
+
+        if (shared_data->flags != OWN_M5)
+            fatal("Shared memory has invalid owner");
+
+        if (shared_data->version != VERSION)
+            fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
+                    shared_data->version);
+
+    }
 }
 
 void

src/cpu/exetrace.hh

@@ -150,6 +150,7 @@ class InstRecord : public Record
         PRINT_REG_DELTA,
         PC_SYMBOL,
         INTEL_FORMAT,
+        LEGION_LOCKSTEP,
         NUM_BITS
     };
 

src/cpu/m5legion_interface.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include <unistd.h>
+
+#define VERSION         0xA1000001
+#define OWN_M5          0x000000AA
+#define OWN_LEGION      0x00000055
+
+/** !!!  VVV Increment VERSION on change VVV !!! **/
+
+typedef struct {
+    uint32_t flags;
+    uint32_t version;
+
+    uint64_t pc;
+    uint64_t instruction;
+    uint64_t intregs[32];
+
+} SharedData;
+
+/** !!! ^^^  Increment VERSION on change ^^^ !!! **/
+

src/cpu/o3/mem_dep_unit.hh

@@ -69,7 +69,7 @@ class MemDepUnit {
     typedef typename Impl::DynInstPtr DynInstPtr;
 
     /** Empty constructor. Must call init() prior to using in this case. */
-    MemDepUnit() {}
+    MemDepUnit();
 
     /** Constructs a MemDepUnit with given parameters. */
     MemDepUnit(Params *params);

src/cpu/o3/mem_dep_unit_impl.hh

@@ -33,6 +33,13 @@
 #include "cpu/o3/inst_queue.hh"
 #include "cpu/o3/mem_dep_unit.hh"
 
+template <class MemDepPred, class Impl>
+MemDepUnit<MemDepPred, Impl>::MemDepUnit()
+    : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
+      storeBarrierSN(0), iqPtr(NULL)
+{
+}
+
 template <class MemDepPred, class Impl>
 MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
     : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
@@ -160,8 +167,12 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
     // producing memrefs/stores.
     InstSeqNum producing_store;
     if (inst->isLoad() && loadBarrier) {
+        DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
+                loadBarrierSN);
         producing_store = loadBarrierSN;
     } else if (inst->isStore() && storeBarrier) {
+        DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
+                storeBarrierSN);
         producing_store = storeBarrierSN;
     } else {
         producing_store = depPred.checkInst(inst->readPC());
@@ -171,10 +182,12 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
 
     // If there is a producing store, try to find the entry.
     if (producing_store != 0) {
+        DPRINTF(MemDepUnit, "Searching for producer\n");
         MemDepHashIt hash_it = memDepHash.find(producing_store);
 
         if (hash_it != memDepHash.end()) {
             store_entry = (*hash_it).second;
+            DPRINTF(MemDepUnit, "Proucer found\n");
         }
     }
 

src/cpu/ozone/cpu.hh

@@ -361,8 +361,8 @@ class OzoneCPU : public BaseCPU
 
     bool interval_stats;
 
-    AlphaITB *itb;
-    AlphaDTB *dtb;
+    TheISA::ITB *itb;
+    TheISA::DTB *dtb;
     System *system;
     PhysicalMemory *physmem;
 #endif

src/cpu/ozone/thread_state.hh

@@ -122,7 +122,7 @@ struct OzoneThreadState : public ThreadState {
 
     MiscReg readMiscRegWithEffect(int misc_reg)
     {
-        return miscRegFile.readRegWithEffect(misc_reg, fault, tc);
+        return miscRegFile.readRegWithEffect(misc_reg, tc);
     }
 
     void setMiscReg(int misc_reg, const MiscReg &val)

src/dev/isa_fake.cc

@@ -50,15 +50,6 @@ IsaFake::IsaFake(Params *p)
     memset(&retData, p->retData, sizeof(retData));
 }
 
-void
-IsaFake::init()
-{
-    // Only init this device if it's connected to anything.
-    if (pioPort)
-        PioDevice::init();
-}
-
-
 Tick
 IsaFake::read(PacketPtr pkt)
 {

src/dev/isa_fake.hh

@@ -80,8 +80,6 @@ class IsaFake : public BasicPioDevice
      * @param data the data to not write.
      */
     virtual Tick write(PacketPtr pkt);
-
-    void init();
 };
 
 #endif // __ISA_FAKE_HH__

src/mem/bus.cc

@@ -240,10 +240,10 @@ Bus::recvRetry(int id)
                 busIdle.reschedule(tickNextIdle);
             }
         }
-        //If we weren't able to drain before, we might be able to now.
-        if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle)
-            drainEvent->process();
     }
+    //If we weren't able to drain before, we might be able to now.
+    if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle)
+        drainEvent->process();
 }
 
 Port *
@@ -521,10 +521,10 @@ Bus::drain(Event * de)
     //waiting. We might be idle but have someone waiting if the device we
     //contacted for a retry didn't actually retry.
     if (curTick >= tickNextIdle && retryList.size() == 0) {
+        return 0;
+    } else {
         drainEvent = de;
         return 1;
-    } else {
-        return 0;
     }
 }
 

src/mem/bus.hh

@@ -257,8 +257,8 @@ class Bus : public MemObject
     Bus(const std::string &n, int bus_id, int _clock, int _width,
         bool responder_set)
         : MemObject(n), busId(bus_id), clock(_clock), width(_width),
-          tickNextIdle(0), busIdle(this), inRetry(false), defaultPort(NULL),
-          responderSet(responder_set)
+          tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false),
+          defaultPort(NULL), responderSet(responder_set)
     {
         //Both the width and clock period must be positive
         if (width <= 0)

src/mem/cache/base_cache.cc

@@ -140,6 +140,9 @@ BaseCache::CachePort::recvRetry()
             }
             waitingOnRetry = false;
         }
+        // Check if we're done draining once this list is empty
+        if (drainList.empty())
+            cache->checkDrain();
     }
     else if (!isCpuSide)
     {
@@ -338,6 +341,10 @@ BaseCache::CacheEvent::process()
         cachePort->drainList.push_back(pkt);
         cachePort->waitingOnRetry = true;
     }
+
+    // Check if we're done draining once this list is empty
+    if (cachePort->drainList.empty())
+        cachePort->cache->checkDrain();
 }
 
 const char *
@@ -599,3 +606,18 @@ BaseCache::regStats()
         ;
 
 }
+
+unsigned int
+BaseCache::drain(Event *de)
+{
+    // Set status
+    if (!canDrain()) {
+        drainEvent = de;
+
+        changeState(SimObject::Draining);
+        return 1;
+    }
+
+    changeState(SimObject::Drained);
+    return 0;
+}

src/mem/cache/base_cache.hh

@@ -105,6 +105,8 @@ class BaseCache : public MemObject
 
         void clearBlocked();
 
+        bool canDrain() { return drainList.empty(); }
+
         bool blocked;
 
         bool mustSendRetry;
@@ -227,6 +229,9 @@ class BaseCache : public MemObject
     /** The number of misses to trigger an exit event. */
     Counter missCount;
 
+    /** The drain event. */
+    Event *drainEvent;
+
   public:
     // Statistics
     /**
@@ -340,7 +345,7 @@ class BaseCache : public MemObject
     BaseCache(const std::string &name, Params &params)
         : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
           slaveRequests(0), blkSize(params.blkSize),
-          missCount(params.maxMisses)
+          missCount(params.maxMisses), drainEvent(NULL)
     {
         //Start ports at null if more than one is created we should panic
         cpuSidePort = NULL;
@@ -477,6 +482,7 @@ class BaseCache : public MemObject
     {
         uint8_t flag = 1<<cause;
         masterRequests &= ~flag;
+        checkDrain();
     }
 
     /**
@@ -512,6 +518,7 @@ class BaseCache : public MemObject
     {
         uint8_t flag = 1<<cause;
         slaveRequests &= ~flag;
+        checkDrain();
     }
 
     /**
@@ -589,6 +596,30 @@ class BaseCache : public MemObject
             return;
         }
     }
+
+    virtual unsigned int drain(Event *de);
+
+    void checkDrain()
+    {
+        if (drainEvent && canDrain()) {
+            drainEvent->process();
+            changeState(SimObject::Drained);
+            // Clear the drain event
+            drainEvent = NULL;
+        }
+    }
+
+    bool canDrain()
+    {
+        if (doMasterRequest() || doSlaveRequest()) {
+            return false;
+        } else if (memSidePort && !memSidePort->canDrain()) {
+            return false;
+        } else if (cpuSidePort && !cpuSidePort->canDrain()) {
+            return false;
+        }
+        return true;
+    }
 };
 
 #endif //__BASE_CACHE_HH__

src/python/m5/__init__.py

@@ -39,6 +39,9 @@ from cc_main import simulate, SimLoopExitEvent
 # import the m5 compile options
 import defines
 
+# define a MaxTick parameter
+MaxTick = 2**63 - 1
+
 # define this here so we can use it right away if necessary
 def panic(string):
     print >>sys.stderr, 'panic:', string
@@ -171,10 +174,10 @@ def switchCpus(cpuList):
 
     for cpu in old_cpus:
         if not isinstance(cpu, objects.BaseCPU):
-            raise TypeError, "%s is not of type BaseCPU", cpu
+            raise TypeError, "%s is not of type BaseCPU" % cpu
     for cpu in new_cpus:
         if not isinstance(cpu, objects.BaseCPU):
-            raise TypeError, "%s is not of type BaseCPU", cpu
+            raise TypeError, "%s is not of type BaseCPU" % cpu
 
     # Drain all of the individual CPUs
     drain_event = cc_main.createCountedDrain()

src/python/m5/main.py

@@ -181,6 +181,8 @@ bool_option("print-cpseq", default=False,
     help="Print correct path sequence numbers in trace output")
 #bool_option("print-reg-delta", default=False,
 #    help="Print which registers changed to what in trace output")
+bool_option("legion-lock", default=False,
+    help="Compare simulator state with Legion simulator every cycle")
 
 options = attrdict()
 arguments = []
@@ -296,6 +298,7 @@ def main():
     objects.ExecutionTrace.print_fetchseq = options.print_fetch_seq
     objects.ExecutionTrace.print_cpseq = options.print_cpseq
     #objects.ExecutionTrace.print_reg_delta = options.print_reg_delta
+    objects.ExecutionTrace.legion_lockstep = options.legion_lock
 
     sys.argv = arguments
     sys.path = [ os.path.dirname(sys.argv[0]) ] + sys.path

src/python/m5/objects/BaseCPU.py

@@ -8,7 +8,6 @@ from Bus import Bus
 class BaseCPU(SimObject):
     type = 'BaseCPU'
     abstract = True
-    mem = Param.MemObject("memory")
 
     system = Param.System(Parent.any, "system object")
     cpu_id = Param.Int("CPU identifier")
@@ -47,7 +46,6 @@ class BaseCPU(SimObject):
         self.icache_port = ic.cpu_side
         self.dcache_port = dc.cpu_side
         self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
-#        self.mem = dc
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
         self.addPrivateSplitL1Caches(ic, dc)

src/python/m5/objects/Tsunami.py

@@ -76,6 +76,7 @@ class Tsunami(Platform):
         self.pchip.pio = bus.port
         self.pciconfig.pio = bus.default
         bus.responder_set = True
+        bus.responder = self.pciconfig
         self.fake_sm_chip.pio = bus.port
         self.fake_uart1.pio = bus.port
         self.fake_uart2.pio = bus.port

src/sim/host.hh

@@ -56,7 +56,7 @@ typedef int64_t Counter;
  */
 typedef int64_t Tick;
 
-const Tick MaxTick = (1LL << 62);
+const Tick MaxTick = (1LL << 63) - 1;
 
 /**
  * Address type

src/sim/main.cc

@@ -309,18 +309,14 @@ finalInit()
  * @return The SimLoopExitEvent that caused the loop to exit.
  */
 SimLoopExitEvent *
-simulate(Tick num_cycles = -1)
+simulate(Tick num_cycles = MaxTick)
 {
     warn("Entering event queue @ %d.  Starting simulation...\n", curTick);
 
-    // Fix up num_cycles.  Special default value -1 means simulate
-    // "forever"... schedule event at MaxTick just to be safe.
-    // Otherwise it's a delta for additional cycles to simulate past
-    // curTick, and thus must be non-negative.
-    if (num_cycles == -1)
-        num_cycles = MaxTick;
-    else if (num_cycles < 0)
+    if (num_cycles < 0)
         fatal("simulate: num_cycles must be >= 0 (was %d)\n", num_cycles);
+    else if (curTick + num_cycles < 0)  //Overflow
+        num_cycles = MaxTick;
     else
         num_cycles = curTick + num_cycles;