fullsys now builds and runs for about one cycle

SConscript:
    easier to fix than temporarily remove
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    mem needed for both fullsys and syscall
dev/baddev.cc:
    fix for new mem system
dev/io_device.cc:
    fix typo
dev/io_device.hh:
    PioDevice needs to be a memobject
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
    fix for new mem systems
dev/platform.cc:
dev/platform.hh:
dev/tsunami.cc:
dev/tsunami.hh:
    rather than the platform have a pointer to pciconfig, go the other
    way so all devices are the same and can have a platform pointer
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart8250.cc:
python/m5/objects/AlphaConsole.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/Device.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/System.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
    fixes for newmem

--HG--
extra : convert_revision : b7b67e19095cca64889f6307725aa2f3d84c7105

python/m5/objects/AlphaConsole.py

@@ -1,9 +1,9 @@
 from m5 import *
-from Device import PioDevice
+from Device import BasicPioDevice
 
-class AlphaConsole(PioDevice):
+class AlphaConsole(BasicPioDevice):
     type = 'AlphaConsole'
     cpu = Param.BaseCPU(Parent.any, "Processor")
     disk = Param.SimpleDisk("Simple Disk")
     sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
-    system = Param.System(Parent.any, "system object")
+    system = Param.AlphaSystem(Parent.any, "system object")

python/m5/objects/BadDevice.py

@@ -1,6 +1,6 @@
 from m5 import *
-from Device import PioDevice
+from Device import BasicPioDevice
 
-class BadDevice(PioDevice):
+class BadDevice(BasicPioDevice):
     type = 'BadDevice'
     devicename = Param.String("Name of device to error on")

python/m5/objects/BaseCPU.py

@@ -2,6 +2,7 @@ from m5 import *
 class BaseCPU(SimObject):
     type = 'BaseCPU'
     abstract = True
+    mem = Param.MemObject("memory")
 
     if build_env['FULL_SYSTEM']:
         dtb = Param.AlphaDTB("Data TLB")
@@ -9,7 +10,6 @@ class BaseCPU(SimObject):
         system = Param.System(Parent.any, "system object")
         cpu_id = Param.Int(-1, "CPU identifier")
     else:
-        mem = Param.MemObject("memory")
         workload = VectorParam.Process("processes to run")
 
     max_insts_all_threads = Param.Counter(0,

python/m5/objects/Device.py

@@ -1,35 +1,14 @@
 from m5 import *
-from FunctionalMemory import FunctionalMemory
+from MemObject import MemObject
 
-# This device exists only because there are some devices that I don't
-# want to have a Platform parameter because it would cause a cycle in
-# the C++ that cannot be easily solved.
-#
-# The real solution to this problem is to pass the ParamXXX structure
-# to the constructor, but with the express condition that SimObject
-# parameter values are not to be available at construction time.  If
-# some further configuration must be done, it must be done during the
-# initialization phase at which point all SimObject pointers will be
-# valid.
-class FooPioDevice(FunctionalMemory):
+class PioDevice(MemObject):
     type = 'PioDevice'
     abstract = True
-    addr = Param.Addr("Device Address")
-    mmu = Param.MemoryController(Parent.any, "Memory Controller")
-    pio_bus = Param.Bus(NULL, "Bus to attach to for PIO")
-    pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
+    platform = Param.Platform(Parent.any, "Platform this device is part of")
+    system = Param.System(Parent.any, "System this device is part of")
 
-class FooDmaDevice(FooPioDevice):
-    type = 'DmaDevice'
+class BasicPioDevice(PioDevice):
+    type = 'BasicPioDevice'
     abstract = True
-    dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")
-
-class PioDevice(FooPioDevice):
-    type = 'PioDevice'
-    abstract = True
-    platform = Param.Platform(Parent.any, "Platform")
-
-class DmaDevice(PioDevice):
-    type = 'DmaDevice'
-    abstract = True
-    dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")
+    pio_addr = Param.Addr("Device Address")
+    pio_latency = Param.Tick(1, "Programmed IO latency in simticks")

python/m5/objects/Pci.py

@@ -1,5 +1,6 @@
 from m5 import *
-from Device import FooPioDevice, DmaDevice
+from Device import BasicPioDevice
+#, DmaDevice
 
 class PciConfigData(SimObject):
     type = 'PciConfigData'
@@ -38,18 +39,18 @@ class PciConfigData(SimObject):
     MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
     MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
 
-class PciConfigAll(FooPioDevice):
+class PciConfigAll(BasicPioDevice):
     type = 'PciConfigAll'
 
-class PciDevice(DmaDevice):
-    type = 'PciDevice'
-    abstract = True
-    addr = 0xffffffffL
-    pci_bus = Param.Int("PCI bus")
-    pci_dev = Param.Int("PCI device number")
-    pci_func = Param.Int("PCI function code")
-    configdata = Param.PciConfigData(Parent.any, "PCI Config data")
-    configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
-
-class PciFake(PciDevice):
-    type = 'PciFake'
+#class PciDevice(DmaDevice):
+#    type = 'PciDevice'
+#    abstract = True
+#    addr = 0xffffffffL
+#    pci_bus = Param.Int("PCI bus")
+#    pci_dev = Param.Int("PCI device number")
+#    pci_func = Param.Int("PCI function code")
+#    configdata = Param.PciConfigData(Parent.any, "PCI Config data")
+#    configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
+#
+#class PciFake(PciDevice):
+#    type = 'PciFake'

python/m5/objects/PhysicalMemory.py

@@ -5,5 +5,3 @@ class PhysicalMemory(Memory):
     type = 'PhysicalMemory'
     range = Param.AddrRange("Device Address")
     file = Param.String('', "memory mapped file")
-    if build_env['FULL_SYSTEM']:
-        mmu = Param.MemoryController(Parent.any, "Memory Controller")

python/m5/objects/System.py

@@ -6,7 +6,6 @@ class System(SimObject):
     if build_env['FULL_SYSTEM']:
         boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
                                              "boot processor frequency")
-        memctrl = Param.MemoryController(Parent.any, "memory controller")
         init_param = Param.UInt64(0, "numerical value to pass into simulator")
         bin = Param.Bool(False, "is this system binned")
         binned_fns = VectorParam.String([], "functions broken down and binned")

python/m5/objects/Tsunami.py

@@ -1,27 +1,27 @@
 from m5 import *
-from Device import FooPioDevice
+from Device import BasicPioDevice
 from Platform import Platform
 
 class Tsunami(Platform):
     type = 'Tsunami'
-    pciconfig = Param.PciConfigAll("PCI configuration")
+#    pciconfig = Param.PciConfigAll("PCI configuration")
     system = Param.System(Parent.any, "system")
 
-class TsunamiCChip(FooPioDevice):
+class TsunamiCChip(BasicPioDevice):
     type = 'TsunamiCChip'
     tsunami = Param.Tsunami(Parent.any, "Tsunami")
 
-class IsaFake(FooPioDevice):
+class IsaFake(BasicPioDevice):
     type = 'IsaFake'
-    size = Param.Addr("Size of address range")
+    pio_size = Param.Addr(0x8, "Size of address range")
 
-class TsunamiIO(FooPioDevice):
+class TsunamiIO(BasicPioDevice):
     type = 'TsunamiIO'
     time = Param.UInt64(1136073600,
         "System time to use (0 for actual time, default is 1/1/06)")
     tsunami = Param.Tsunami(Parent.any, "Tsunami")
     frequency = Param.Frequency('1024Hz', "frequency of interrupts")
 
-class TsunamiPChip(FooPioDevice):
+class TsunamiPChip(BasicPioDevice):
     type = 'TsunamiPChip'
     tsunami = Param.Tsunami(Parent.any, "Tsunami")

python/m5/objects/Uart.py

@@ -1,11 +1,10 @@
 from m5 import *
-from Device import PioDevice
+from Device import BasicPioDevice
 
-class Uart(PioDevice):
+class Uart(BasicPioDevice):
     type = 'Uart'
     abstract = True
-    console = Param.SimConsole(Parent.any, "The console")
-    size = Param.Addr(0x8, "Device size")
+    sim_console = Param.SimConsole(Parent.any, "The console")
 
 class Uart8250(Uart):
     type = 'Uart8250'