gpu-compute,arch-vega: Overhaul HWRegs, setreg, getreg

These instructions are supposed to be read/writing special shader
hardware registers. Currently they are getting/setting to an SGPR. This
results in getting incorrect registers at best and clobbering an SGPR
being used by an application at worst. Furthermore, some registers need
to be set in the shader and the application will never (can never) set
them.

This patch overhauls the getreg/setreg instructions to use different
storage in the shader. The values will be updated either via setreg from
an application (e.g., mode register) or set by a PM4 MAP_PROCESS.

Change-Id: Ie5e5d552bd04dc47f5b35b5ee40a569ae345abac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61655
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Matthew Poremba
2022-07-24 09:22:14 -07:00
parent 5c7514c81c
commit f65f5a8981
4 changed files with 106 additions and 14 deletions

View File

@@ -88,6 +88,9 @@ class Shader : public ClockedObject
ApertureRegister _scratchApe;
Addr shHiddenPrivateBaseVmid;
// Hardware regs accessed by getreg/setreg instructions, set by queues
std::unordered_map<int, uint32_t> hwRegs;
// Number of active Cus attached to this shader
int _activeCus;
@@ -109,6 +112,18 @@ class Shader : public ClockedObject
ThreadContext *gpuTc;
BaseCPU *cpuPointer;
void
setHwReg(int regIdx, uint32_t val)
{
hwRegs[regIdx] = val;
}
uint32_t
getHwReg(int regIdx)
{
return hwRegs[regIdx];
}
const ApertureRegister&
gpuVmApe() const
{