gpu-compute,arch-vega: Overhaul HWRegs, setreg, getreg
These instructions are supposed to be read/writing special shader hardware registers. Currently they are getting/setting to an SGPR. This results in getting incorrect registers at best and clobbering an SGPR being used by an application at worst. Furthermore, some registers need to be set in the shader and the application will never (can never) set them. This patch overhauls the getreg/setreg instructions to use different storage in the shader. The values will be updated either via setreg from an application (e.g., mode register) or set by a PM4 MAP_PROCESS. Change-Id: Ie5e5d552bd04dc47f5b35b5ee40a569ae345abac Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61655 Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
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@@ -88,6 +88,9 @@ class Shader : public ClockedObject
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ApertureRegister _scratchApe;
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Addr shHiddenPrivateBaseVmid;
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// Hardware regs accessed by getreg/setreg instructions, set by queues
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std::unordered_map<int, uint32_t> hwRegs;
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// Number of active Cus attached to this shader
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int _activeCus;
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@@ -109,6 +112,18 @@ class Shader : public ClockedObject
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ThreadContext *gpuTc;
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BaseCPU *cpuPointer;
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void
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setHwReg(int regIdx, uint32_t val)
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{
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hwRegs[regIdx] = val;
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}
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uint32_t
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getHwReg(int regIdx)
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{
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return hwRegs[regIdx];
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}
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const ApertureRegister&
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gpuVmApe() const
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{
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