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arch-x86,arch-arm: Remove static variables in decoders (#1643)

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There were a number of variables in the arm and x86 decoders that are
static (e.g., the decode cache). It's a bit interesting that this
doesn't cause problems with multiple cores since each core has its own
decoder.

However, this causes segfaults if you run different cores on different
*host* threads. We are experimenting with running gem5 with multiple
host thread (i.e., in parallel), and removing these static variables
resolves the segfault.

This change also adds const to any other static variables to ensure that
they cannot be modified.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Jason Lowe-Power
2024-10-17 08:17:34 -07:00
committed by GitHub
parent deb8f983a1
commit f55a4ce989
4 changed files with 13 additions and 20 deletions
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2
src/arch/arm/decoder.cc
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@@ -53,8 +53,6 @@ namespace gem5
namespace ArmISA
{
GenericISA::BasicDecodeCache<Decoder, ExtMachInst> Decoder::defaultCache;
Decoder::Decoder(const ArmDecoderParams &params)
: InstDecoder(params, &data),
dvmEnabled(params.dvm_enabled),

2
src/arch/arm/decoder.hh
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@@ -94,7 +94,7 @@ class Decoder : public InstDecoder
enums::DecoderFlavor decoderFlavor;
/// A cache of decoded instruction objects.
static GenericISA::BasicDecodeCache<Decoder, ExtMachInst> defaultCache;
GenericISA::BasicDecodeCache<Decoder, ExtMachInst> defaultCache;
friend class GenericISA::BasicDecodeCache<Decoder, ExtMachInst>;
/**

5
src/arch/x86/decoder.cc
View File

@@ -41,8 +41,6 @@ namespace gem5
namespace X86ISA
{
X86ISAInst::MicrocodeRom Decoder::microcodeRom;
Decoder::State
Decoder::doResetState()
{
@@ -671,9 +669,6 @@ Decoder::doImmediateState()
return nextState;
}
Decoder::InstBytes Decoder::dummy;
Decoder::InstCacheMap Decoder::instCacheMap;
StaticInstPtr
Decoder::decode(ExtMachInst mach_inst, Addr addr)
{

24
src/arch/x86/decoder.hh
View File

@@ -60,19 +60,19 @@ class Decoder : public InstDecoder
// These are defined and documented in decoder_tables.cc
static const uint8_t SizeTypeToSize[3][10];
typedef const uint8_t ByteTable[256];
static ByteTable Prefixes[2];
static const ByteTable Prefixes[2];
static ByteTable UsesModRMOneByte;
static ByteTable UsesModRMTwoByte;
static ByteTable UsesModRMThreeByte0F38;
static ByteTable UsesModRMThreeByte0F3A;
static const ByteTable UsesModRMOneByte;
static const ByteTable UsesModRMTwoByte;
static const ByteTable UsesModRMThreeByte0F38;
static const ByteTable UsesModRMThreeByte0F3A;
static ByteTable ImmediateTypeOneByte;
static ByteTable ImmediateTypeTwoByte;
static ByteTable ImmediateTypeThreeByte0F38;
static ByteTable ImmediateTypeThreeByte0F3A;
static const ByteTable ImmediateTypeOneByte;
static const ByteTable ImmediateTypeTwoByte;
static const ByteTable ImmediateTypeThreeByte0F38;
static const ByteTable ImmediateTypeThreeByte0F3A;
static X86ISAInst::MicrocodeRom microcodeRom;
X86ISAInst::MicrocodeRom microcodeRom;
protected:
using MachInst = uint64_t;
@@ -88,7 +88,7 @@ class Decoder : public InstDecoder
{}
};
static InstBytes dummy;
InstBytes dummy;
// The bytes to be predecoded.
MachInst fetchChunk;
@@ -244,7 +244,7 @@ class Decoder : public InstDecoder
decode_cache::InstMap<ExtMachInst> *instMap = nullptr;
typedef std::unordered_map<
CacheKey, decode_cache::InstMap<ExtMachInst> *> InstCacheMap;
static InstCacheMap instCacheMap;
InstCacheMap instCacheMap;
StaticInstPtr decodeInst(ExtMachInst mach_inst);