diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index d9738d22b0..d9e36758f1 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -406,7 +406,8 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t *data, unsigned size,
             }
             dcache_access = true;
 
-            assert(!pkt.isError());
+            panic_if(pkt.isError(), "Data fetch (%s) failed: %s",
+                    pkt.getAddrRange().to_string(), pkt.print());
 
             if (req->isLLSC()) {
                 thread->getIsaPtr()->handleLockedRead(req);
@@ -508,8 +509,8 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
                     threadSnoop(&pkt, curThread);
                 }
                 dcache_access = true;
-                assert(!pkt.isError());
-
+                panic_if(pkt.isError(), "Data write (%s) failed: %s",
+                        pkt.getAddrRange().to_string(), pkt.print());
                 if (req->isSwap()) {
                     assert(res && curr_frag_id == 0);
                     memcpy(res, pkt.getConstPtr<uint8_t>(), size);
@@ -597,7 +598,8 @@ AtomicSimpleCPU::amoMem(Addr addr, uint8_t* data, unsigned size,
 
         dcache_access = true;
 
-        assert(!pkt.isError());
+        panic_if(pkt.isError(), "Atomic access (%s) failed: %s",
+                pkt.getAddrRange().to_string(), pkt.print());
         assert(!req->isLLSC());
     }
 
@@ -752,7 +754,8 @@ AtomicSimpleCPU::fetchInstMem()
     pkt.dataStatic(decoder->moreBytesPtr());
 
     Tick latency = sendPacket(icachePort, &pkt);
-    assert(!pkt.isError());
+    panic_if(pkt.isError(), "Instruction fetch (%s) failed: %s",
+            pkt.getAddrRange().to_string(), pkt.print());
 
     return latency;
 }
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index da3e0c0113..c7e63efa84 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -826,7 +826,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
 
     // received a response from the icache: execute the received
     // instruction
-    assert(!pkt || !pkt->isError());
+    panic_if(pkt && pkt->isError(), "Instruction fetch (%s) failed: %s",
+            pkt->getAddrRange().to_string(), pkt->print());
     assert(_status == IcacheWaitResponse);
 
     _status = BaseSimpleCPU::Running;
@@ -950,7 +951,8 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
 
     // received a response from the dcache: complete the load or store
     // instruction
-    assert(!pkt->isError());
+    panic_if(pkt->isError(), "Data access (%s) failed: %s",
+            pkt->getAddrRange().to_string(), pkt->print());
     assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
            pkt->req->getFlags().isSet(Request::NO_ACCESS));